Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) External QFN 16

FEATURES APPLICATIONS

DESCRIPTION

REF−

+IN

REF+

SDI

SCLK

SDO

CDAC

SAR

COMPARATOR

OUTPUT

LATCH

and

3−STATE

DRIVER

CONVERSION

and

CONTROL

LOGIC

−IN

+IN1

+IN0

COM

OSC

ADS8330 ADS8329

FS/CS

CONVST

EOC/INT/CDI

ADS8329

ADS8330

www.ti.com

................................................................................................................................................... SLAS516C – DECEMBER 2006 – REVISED JULY 2009

LOW-POWER, 16-BIT, 1-MHz, SINGLE/DUAL UNIPOLAR INPUT,

ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL INTERFACE

• Communications

• 2.7-V to 5.5-V Analog Supply, Low Power:

• Transducer Interface

– 15.5 mW (1 MHz, +VA = 3 V, +VBD = 1.8 V)

• Medical Instruments

• 1-MHz Sampling Rate 3 V ≤ +VA ≤ 5.5 V,

• Magnetometers

900-kHz Sampling Rate 2.7 V ≤ +VA ≤ 3 V

• Industrial Process Control

• Excellent DC Performance:

• Data Acquisition Systems

± 1.0 LSB Typ, ± 1.75 LSB Max INL

± 0.5 LSB Typ, ± 1 LSB Max DNL

• Automatic Test Equipment

16-Bit NMC Over Temperature

± 0.5 mV Max Offset Error at 3 V

± 1 mV Max Offset Error at 5 V

The ADS8329 is a low-power, 16-bit, 1-MSPS

• Excellent AC Performance at f

= 10 kHz with

analog-to-digital converter (ADC) with a unipolar

93 dB SNR, 105 dB SFDR, – 102 dB THD

input. The device includes a 16-bit capacitor-based

SAR ADC with inherent sample-and-hold.

• Built-In Conversion Clock (CCLK)

• 1.65 V to 5.5 V I/O Supply: The ADS8330 is based on the same core and

includes a 2-to-1 input MUX with programmable

SPI/DSP Compatible Serial

option of TAG bit output. Both the ADS8329 and

SCLK up to 50 MHz

ADS8330 offer a high-speed, wide voltage serial

• Comprehensive Power-Down Modes:

interface and are capable of chain mode operation

Deep Power-Down

when multiple converters are used.

Nap Power-Down

These converters are available in 4 × 4 QFN and

Auto Nap Power-Down

16-pin TSSOP packages, and are fully specified for

• Unipolar Input Range: 0 V to V

REF

operation over the industrial – 40 ° C to +85 ° C

• Software Reset

temperature range.

• Global CONVST (Independent of CS)

Low Power, High-Speed SAR Converter Family

• Programmable Status/Polarity EOC/ INT

Type/Speed 500 kSPS 1 MSPS

• 16-Pin 4 × 4 QFN and 16-Pin TSSOP Packages

Single ADS8327 ADS8329

• Multi-Chip Daisy Chain Mode

16-bit single-ended

Dual ADS8328 ADS8330

• Programmable TAG Bit Output

Single — ADS7279

14-bit single-ended

• Auto/Manual Channel Select Mode (ADS8330)

Dual — ADS7280

Single — ADS7229

12-bit single ended

Dual — ADS7230

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2 All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (50 pages)

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ADS8329 ADS8330 www.ti.com ................................................................................................................................................... SLAS516C – DECEMBER 2006 – REVISED JULY 2009 LOW-POWER, 16-BIT, 1-MHz, SINGLE/DUAL UNIPOLAR INPUT, ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL INTERFACE FEATURES APPLICATIONS • 2.7-V to 5.5-V Analog Supply, Low Power: – 15.5 mW (1 MHz, +VA = 3 V, +VBD = 1.8 V) • 1-MHz Sampling Rate 3 V ≤ +VA ≤ 5.5 V, 900-kHz Sampling Rate 2.
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ADS8329 ADS8330 SLAS516C – DECEMBER 2006 – REVISED JULY 2009 ................................................................................................................................................... www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION (1) MAXIMUM INTEGRAL LINEARITY (LSB) MODEL ADS8329I ±2.
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ADS8329 ADS8330 www.ti.com ................................................................................................................................................... SLAS516C – DECEMBER 2006 – REVISED JULY 2009 ELECTRICAL CHARACTERISTICS TA = –40°C to 85°C, +VA = 4.5 V to 5.5 V, +VBD = 1.65 V to 5.5 V, VREF = 5 V, and fSAMPLE = 1 MHz, unless otherwise noted.
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ADS8329 ADS8330 SLAS516C – DECEMBER 2006 – REVISED JULY 2009 ................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS (continued) TA = –40°C to 85°C, +VA = 4.5 V to 5.5 V, +VBD = 1.65 V to 5.5 V, VREF = 5 V, and fSAMPLE = 1 MHz, unless otherwise noted.
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ADS8329 ADS8330 www.ti.com ................................................................................................................................................... SLAS516C – DECEMBER 2006 – REVISED JULY 2009 ELECTRICAL CHARACTERISTICS TA = –40°C to 85°C, +VA = 2.7 V to 3.6 V, +VBD = 1.65 V to 1.5×(+VA), VREF = 2.5 V, fSAMPLE = 1 MHz for 3 V ≤ +VA ≤ 3.6 V, fSAMPLE = 900 kHz for 3 V < +VA ≤ 2.
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ADS8329 ADS8330 SLAS516C – DECEMBER 2006 – REVISED JULY 2009 ................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS (continued) TA = –40°C to 85°C, +VA = 2.7 V to 3.6 V, +VBD = 1.65 V to 1.5×(+VA), VREF = 2.5 V, fSAMPLE = 1 MHz for 3 V ≤ +VA ≤ 3.6 V, fSAMPLE = 900 kHz for 3 V < +VA ≤ 2.
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ADS8329 ADS8330 www.ti.com ................................................................................................................................................... SLAS516C – DECEMBER 2006 – REVISED JULY 2009 ELECTRICAL CHARACTERISTICS (continued) TA = –40°C to 85°C, +VA = 2.7 V to 3.6 V, +VBD = 1.65 V to 1.5×(+VA), VREF = 2.5 V, fSAMPLE = 1 MHz for 3 V ≤ +VA ≤ 3.6 V, fSAMPLE = 900 kHz for 3 V < +VA ≤ 2.
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ADS8329 ADS8330 SLAS516C – DECEMBER 2006 – REVISED JULY 2009 ................................................................................................................................................... www.ti.com TIMING CHARACTERISTICS All specifications typical at –40°C to 85°C and +VA = +VBD = 5 V. (1) (2) PARAMETER fCCLK Frequency, conversion clock, CCLK MIN External, fCCLK = 1/2 fSCLK 0.5 Internal, fCCLK = 1/2 fSCLK 21 TYP MAX UNIT 21 MHz 22.9 24.
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ADS8329 ADS8330 www.ti.com ................................................................................................................................................... SLAS516C – DECEMBER 2006 – REVISED JULY 2009 TIMING CHARACTERISTICS All specifications typical at –40°C to 85°C, +VA = 2.7 V, +VBD = 1.8 V (unless otherwise noted) PARAMETER fCCLK Frequency, conversion clock, CCLK (1) (2) MIN TYP MAX External, 3 V ≤ +VA ≤ 3.6 V, fCCLK = 1/2 fSCLK 0.5 21 External, 2.
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ADS8329 ADS8330 SLAS516C – DECEMBER 2006 – REVISED JULY 2009 ................................................................................................................................................... www.ti.
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ADS8329 ADS8330 www.ti.com ................................................................................................................................................... SLAS516C – DECEMBER 2006 – REVISED JULY 2009 ADS8329 Terminal Functions NO. QFN TSSOP I/O AGND NAME 15 5 — Analog ground BDGND 8 14 — Interface ground CONVST 3 9 I Freezes sample and hold, starts conversion with next rising edge of internal clock Status output.
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ADS8329 ADS8330 SLAS516C – DECEMBER 2006 – REVISED JULY 2009 ................................................................................................................................................... www.ti.
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ADS8329 ADS8330 www.ti.com ...................................................................................................................................................
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ADS8329 ADS8330 SLAS516C – DECEMBER 2006 – REVISED JULY 2009 ................................................................................................................................................... www.ti.
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ADS8329 ADS8330 www.ti.com ................................................................................................................................................... SLAS516C – DECEMBER 2006 – REVISED JULY 2009 TYPICAL CHARACTERISTICS At –40°C to 85°C, VREF [REF+ – (REF–)] = 5 V when +VA = +VBD = 5 V or VREF [REF+ – (REF–)] = 2.5 V when +VA = +VBD = 3 V, fSCLK = 42 MHz, or VREF = 2.5 when +VA = +VBD = 2.7 V, fSCLK = 37.
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ADS8329 ADS8330 SLAS516C – DECEMBER 2006 – REVISED JULY 2009 ................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) INTEGRAL NONLINEARITY vs EXTERNAL CLOCK FREQUENCY OFFSET VOLTAGE vs FREE-AIR TEMPERATURE 2 OFFSET VOLTAGE vs SUPPLY VOLTAGE 1 1 +VA = 3 V 1.5 MAX 0 MIN Offset Voltage - mV 0.5 -0.5 0.8 0.
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ADS8329 ADS8330 www.ti.com ...................................................................................................................................................
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ADS8329 ADS8330 SLAS516C – DECEMBER 2006 – REVISED JULY 2009 ................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) EFFECTIVE NUMBER OF BITS vs FREE-AIR TEMPERATURE INTERNAL CLOCK FREQUENCY vs SUPPLY VOLTAGE 24 15.50 +VA = 5 V 15 +VA = 3 V 14.50 14 -40 -25 -10 5 20 35 50 65 24 23.
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ADS8329 ADS8330 www.ti.com ................................................................................................................................................... SLAS516C – DECEMBER 2006 – REVISED JULY 2009 TYPICAL CHARACTERISTICS (continued) ANALOG SUPPLY CURRENT vs FREE-AIR TEMPERATURE 0.4 Analog Supply Current - mA NAP Mode 0.36 +VA = 5 V 0.32 0.28 +VA = 3 V 0.24 0.2 -40 -25 -10 5 20 35 50 65 TA - Free-Air Temperature - ºC 80 Figure 40. INL 1.75 1.5 +VA = 5 V INL - Bits 1.0 0.
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ADS8329 ADS8330 SLAS516C – DECEMBER 2006 – REVISED JULY 2009 ................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) INL 1.75 1.5 +VA = 3 V INL - Bits 1.0 0.5 0 -0.5 -1.0 -1.5 -1.75 0 10000 20000 30000 Code 40000 50000 60000 Figure 43. DNL 1 +VA = 3 V DNL - Bits 0.5 0 -0.5 -1 0 10000 20000 30000 Code 40000 50000 60000 Figure 44.
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ADS8329 ADS8330 www.ti.com ................................................................................................................................................... SLAS516C – DECEMBER 2006 – REVISED JULY 2009 TYPICAL CHARACTERISTICS (continued) FFT 0 10 kHz Input, +VA = 3 V, fs = 1 MSPS, Vref = 2.5 V -20 Amplitude - dB -40 -60 -80 -100 -120 -140 -160 0 100 200 300 400 500 f - Frequency - kHz Figure 46. FFT 0 100 kHz Input, +VA = 3 V, fs = 1 MSPS, Vref = 2.
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ADS8329 ADS8330 SLAS516C – DECEMBER 2006 – REVISED JULY 2009 ................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) FFT 20 0 10 kHz Input, +VA = 5 V, fs = 1 MSPS, Vref = 5 V Amplitude - dB -20 -40 -60 -80 -100 -120 -140 -160 0 100 200 300 400 500 f - Frequency - kHz Figure 49.
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ADS8329 ADS8330 www.ti.com ................................................................................................................................................... SLAS516C – DECEMBER 2006 – REVISED JULY 2009 The (peak) input current through the analog inputs depends upon a number of factors: sample rate, input voltage, and source impedance. The current into the ADS8329/30 charges the internal capacitor array during the sample period.
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ADS8329 ADS8330 SLAS516C – DECEMBER 2006 – REVISED JULY 2009 ................................................................................................................................................... www.ti.com Input Signal (0 V to 4 V) 5V ADS8329 +VA THS4031 20 W +IN 470 pF 50 W -IN 20 W Figure 52. Unipolar Input Drive Configuration 5V ADS8329 1V DC +VA THS4031 600 W 20 W +IN 470 pF Input Signal (-2 V to 2 V) 600 W -IN 20 W Figure 53.
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ADS8329 ADS8330 www.ti.com ................................................................................................................................................... SLAS516C – DECEMBER 2006 – REVISED JULY 2009 The duty cycle of SCLK is not critical as long as it meets the minimum high and low time requirements of 8 ns.
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ADS8329 ADS8330 SLAS516C – DECEMBER 2006 – REVISED JULY 2009 ................................................................................................................................................... www.ti.com Status Output EOC/INT When the status pin is programmed as EOC and the polarity is set as active low, the pin works in the following manner: The EOC output goes LOW immediately following CONVST going LOW when manual trigger is programmed.
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ADS8329 ADS8330 www.ti.com ................................................................................................................................................... SLAS516C – DECEMBER 2006 – REVISED JULY 2009 Deep Power-Down Mode Deep power-down mode can be activated by writing to configuration register bit CFR_D2. When the device is in deep power-down mode, all blocks except the interface are in power-down. The external SCLK is blocked to the analog block.
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ADS8329 ADS8330 SLAS516C – DECEMBER 2006 – REVISED JULY 2009 ................................................................................................................................................... www.ti.
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ADS8329 ADS8330 www.ti.com ...................................................................................................................................................
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ADS8329 ADS8330 SLAS516C – DECEMBER 2006 – REVISED JULY 2009 ................................................................................................................................................... www.ti.com DIGITAL INTERFACE The serial clock is designed to accommodate the latest high-speed processors with an SCLK frequency up to 50 MHz. Each cycle is started with the falling edge of FS/CS.
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ADS8329 ADS8330 www.ti.com ................................................................................................................................................... SLAS516C – DECEMBER 2006 – REVISED JULY 2009 Configuring the Converter and Default Mode The converter can be configuring with command 1110b (write to the CFR) or command 1111b (default mode). A write to the CFR requires a 4-bit command followed by 12-bits of data. A 4-bit command takes effect at the 4th falling edge of SCLK.
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ADS8329 ADS8330 SLAS516C – DECEMBER 2006 – REVISED JULY 2009 ................................................................................................................................................... www.ti.com The falling edge of FS/CS should not be placed at the precise moment (minimum of at least one conversion clock (CCLK) delay) at the end of a conversion (by default when EOC goes high), otherwise the data is corrupt.
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ADS8329 ADS8330 www.ti.com ................................................................................................................................................... SLAS516C – DECEMBER 2006 – REVISED JULY 2009 Micro Controller INT GPIO1 GPIO2 SDI SCLK CONVST CS ADS8329 #1 SDO EOC/INT SDOSCLK GPIO3 SDI SCLK CONVST CS ADS8329 #3 CDI SDO SDI SCLK CONVST CS ADS8329 #2 CDI SDO Program device #1 CFR_D[7:5] = XX0b SDI Program device #2 and #3 CFR_D[7:5] = XX1b Figure 59.
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ADS8329 ADS8330 SLAS516C – DECEMBER 2006 – REVISED JULY 2009 ................................................................................................................................................... www.ti.com Care must be given to handle the multiple CS signals when the converters are operating in chain mode. The different chip select signals must be low for the entire data transfer (in this example 48 bits for three converters).
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ADS8329 ADS8330 www.ti.com ................................................................................................................................................... SLAS516C – DECEMBER 2006 – REVISED JULY 2009 Cascaded Manual Trigger/Read While Sampling (Use internal CCLK, EOC active low and INT active low) CS held low during the N times 16 bits transfer cycle. Note : old data shown.
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ADS8329 ADS8330 SLAS516C – DECEMBER 2006 – REVISED JULY 2009 ................................................................................................................................................... www.ti.com SCLK skew between converters and data path delay through the converters configured in chain mode can affect the maximum frequency of SCLK. The delay can also be affected by supply voltage and loading. It may be necessary to slow down the SCLK when the devices are configured in chain mode.
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ADS8329 ADS8330 www.ti.com ................................................................................................................................................... SLAS516C – DECEMBER 2006 – REVISED JULY 2009 When the device is powered up, the POR sets the device to default mode when AVDD reaches 1.5V.
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ADS8329 ADS8330 SLAS516C – DECEMBER 2006 – REVISED JULY 2009 ................................................................................................................................................... www.ti.com APPLICATION INFORMATION TYPICAL CONNECTION Analog +5 V 4.7 mF AGND Ext Ref Input 22 mF Analog Input AGND +VA REF+ REF− AGND IN+ IN− Host Processor FS/CS SDO SDI SCLK Interface Supply +1.8 V ADS8329 BDGND CONVST 4.7 mF EOC/INT +VBD Figure 66.
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ADS8329 ADS8330 www.ti.com ................................................................................................................................................... SLAS516C – DECEMBER 2006 – REVISED JULY 2009 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (March 2008) to Revision C ..................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 11-Apr-2013 Status (1) ADS8330IRSATG4 ACTIVE Package Type Package Pins Package Drawing Qty QFN RSA 16 250 Eco Plan Lead/Ball Finish (2) Green (RoHS & no Sb/Br) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) CU NIPDAU Level-2-260C-1 YEAR (4) -40 to 85 ADS 8330I A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADS8329IBPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 ADS8329IBRSAR QFN RSA 16 3000 330.0 12.4 4.3 4.3 1.5 8.0 12.0 Q2 ADS8329IBRSAT QFN RSA 16 250 180.0 12.4 4.3 4.3 1.5 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS8329IBPWR ADS8329IBRSAR TSSOP PW 16 2000 367.0 367.0 35.0 QFN RSA 16 3000 338.1 338.1 20.6 ADS8329IBRSAT QFN RSA 16 250 210.0 185.0 35.0 ADS8329IPWR TSSOP PW 16 2000 367.0 367.0 35.0 ADS8329IRSAR QFN RSA 16 2000 338.1 338.1 20.6 ADS8329IRSAT QFN RSA 16 250 210.0 185.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.