Datasheet

14
ADS1250
®
t
6
12 19
OUT
LSB
OUT
MSB
DOUT
SCLK
CS
DRDY
CLK
20 21 22 23 24
t
5
t
9
t
10
t
11
t
12
t
7
t
8
FIGURE 16. Method 1: Four-Wire Interface Using Noncontinuous SCLK.
There are three basic methods of receiving data from the
ADS1250. The first two methods involve a four-wire inter-
face and the third method is a three-wire interface.
Method 1: Four-Wire Interface
The most common method of receiving data is using a
simple four-wire interface (CS, SCLK, DOUT, and DRDY).
The DRDY line will pulse LOW after the DOR is updated.
The processor would then take CS LOW to select the device
for communication. Once CS is taken LOW, the DOUT
would be driven to the level dictated by the MSB of the data
output register. The processor would provide 20 (or 24)
SCLKs to read the contents of the DOR. The data bits in the
DOR are shifted out on the DOUT pin after the falling edge
of SCLK. If more than 20 bits of data are read, the data is 0
padded. Taking CS HIGH will take DOUT to a high-
impedance state. The timing for the data transfer is shown in
Figure 16 (see Table III). A simple four-wire interface using
this method is shown in Figure 17. The P1.0 output from the
8xC51 is a free-running clock.
FIGURE 17. Four-Wire Interface to an 8xC51.
DV
DD
DV
DD
8xC51
P1.0 / T2
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
P3.0
P3.1
P3.2 / INT0
P3.3
P3.4
P3.5
P3.6
P3.7
XTAL2
XTAL1
V
SS
V
CC
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
EA
ALE
PSEN
P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
P2.1
P2.0
DGND
C1
XTAL
C2
+V
IN
–V
IN
AGND
+V
S
V
REF
DSYNC
+V
D
DGND
DGND
G1
G0
CS
DRDY
CLK
SCLK
DOUT
DV
DD
V
REF
Circuit
AGND
AV
DD
DGND
DGND
ADS1250