Datasheet

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20-Bit Data Acquisition System

ANALOG-TO-DIGITAL CONVERTER

ADS1250

FEATURES

● 20 BITS NO MISSING CODES

● 18 BITS EFFECTIVE RESOLUTION UP TO

25kHz DATA RATE

● LOW NOISE: 2.8ppm at PGA = 1

● DIFFERENTIAL INPUTS

● INL: 0.002% (MAX)

● PROGRAMMABLE FULL SCALE

● I/O CONTROLLED PGA: 1, 2, 4, 8

● EXTERNAL REFERENCE

DESCRIPTION

The ADS1250 is a precision, wide dynamic range,

delta-sigma, analog-to-digital converter with 20-bit

resolution operating from a single +5V supply. The

delta-sigma architecture is used for wide dynamic

range and to guarantee 20 bits of no missing code

performance. An effective resolution of 18 bits (2.8ppm

of rms noise) is achieved for conversion rates up to

25kHz. The dynamic range of the converter is further

increased by providing a low-noise Programmable

Gain Amplifier (PGA) with gain stages of 1, 2, 4, or

8 for low level input signals.

The ADS1250 is designed for high-resolution mea-

surement applications in cardiac diagnostics, smart

transmitters, industrial process control, weigh scales,

chromatography and portable instrumentation. The

converter includes a flexible synchronous serial inter-

face and offers a three-wire control mode for low-cost

isolation.

The ADS1250 is a single-channel converter and is

offered in an SOL-16 package.

APPLICATIONS

● CARDIAC DIAGNOSTICS

● DIRECT THERMOCOUPLE INTERFACE

● BLOOD ANALYSIS

● INFRARED PYROMETER

● LIQUID/GAS CHROMATOGRAPHY

● PRECISION PROCESS CONTROL

1999 Burr-Brown Corporation PDS-1520B Printed in U.S.A. December, 1999

International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111

Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132

4th-Order

∆Σ

Modulator

Digital

Filter

Serial

Output

Control

PGA

CLK

REF

SCLK

DRDY

DOUT

AGND

DSYNC

DGND

–V

–

ADS1250

For most current data sheet and other product

information, visit www.burr-brown.com

SBAS114

Summary of content (24 pages)

PAGE 1
® ADS ADS1250 125 0 For most current data sheet and other product information, visit www.burr-brown.com 20-Bit Data Acquisition System ANALOG-TO-DIGITAL CONVERTER FEATURES DESCRIPTION ● 20 BITS NO MISSING CODES ● 18 BITS EFFECTIVE RESOLUTION UP TO 25kHz DATA RATE ● LOW NOISE: 2.8ppm at PGA = 1 ● DIFFERENTIAL INPUTS ● INL: 0.
PAGE 2
SPECIFICATIONS All specifications at TMIN to TMAX, VD = VS = +5V, CLK = 9.6MHz, PGA = 1, and VREF = 4.096, unless otherwise specified.
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ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS Analog Input: Current ................................................ ±100mA, Momentary ±10mA, Continuous Voltage ....................................... AGND –0.3V to VS + 0.3V VS to VD .................................................................................... –0.3V to 6V VS to AGND ............................................................................ –0.3V to 6V VD to DGND ......................................................
PAGE 4
PIN CONFIGURATION Top View SOL-16 +VIN 1 16 DGND –VIN 2 15 G1 (MSB) AGND 3 14 G0 (LSB) +VS 4 13 CS ADS1250 VREF 5 12 DRDY DSYNC 6 11 CLK +VD 7 10 SCLK DGND 8 9 DOUT PIN DESCRIPTIONS PIN NAME 1 +VIN Analog Input: Positive Input of the Differential Analog Input. 2 –VIN Analog Input: Negative Input of the Differential Analog Input. 3 AGND 4 +VS 5 VREF 6 DSYNC PIN DESCRIPTION Analog Input: Analog Ground. Analog Input: Analog Power Supply Voltage, +5V.
PAGE 5
TYPICAL PERFORMANCE CURVES At TA = +25°C, VD = VS = +5V, CLK = 9.6MHz, PGA = 1, and VREF = 4.096, unless otherwise specified. EFFECTIVE RESOLUTION vs DATA OUTPUT RATE RMS NOISE vs DATA OUTPUT RATE 20.0 4.0 Effective Resolution Bits (rms) 3.5 RMS Noise (ppm of FS) PGA = 8 PGA = 4 3.0 2.5 PGA = 2 PGA = 1 2.0 1.5 1.0 0.5 PGA = 1 19.0 PGA = 2 18.0 PGA = 4 PGA = 8 17.0 16.0 0.
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TYPICAL PERFORMANCE CURVES (Cont.) At TA = +25°C, VD = VS = +5V, CLK = 9.6MHz, PGA = 1, and VREF = 4.096, unless otherwise specified.
PAGE 7
TYPICAL PERFORMANCE CURVES (Cont.) At TA = +25°C, VD = VS = +5V, CLK = 9.6MHz, PGA = 1, and VREF = 4.096, unless otherwise specified. TYPICAL FFT ANALYSIS OF THE 1kHz fS INPUT SIGNAL (PGA = 4) POWER DISSIPATION vs CLK FREQUENCY (PGA = 1) 0 100 –40 80 Dynamic Range (dB) Power Dissipation (mW) –20 60 40 –60 –80 –100 –120 –140 –160 20 –180 –200 0 0.0 2.0 4.0 6.0 8.0 0 10.
PAGE 8
THEORY OF OPERATION Additionally, a lower gain setting (G) decreases the sampling capacitor size, which results in a higher analog input impedance. This can be seen in the following equation: The ADS1250 is a precision, high dynamic range, 20-bit, delta-sigma, A/D converter capable of achieving very highresolution digital results at high data rates. The analog input signal is continuously sampled at a rate determined by the frequency of the system clock (CLK).
PAGE 9
DELTA-SIGMA MODULATOR The modulator clock is generated by dividing the system clock by 6. With a nominal system clock frequency of 9.6MHz, the modulator clock frequency is 1.6MHz (9.6MHz / 6). The output from the modulator is oversampled 64 times by the digital filter. Therefore, with 1.6MHz modulator clock (derived from a 9.6MHz system clock), the data output rate is 25kHz (1.6MHz / 64). The data output rate scales directly with the system clock frequency, as shown in Table II.
PAGE 10
There is an additional benefit in using a lower data output rate. It will provide better rejection of signals in the frequency band of interest. For example, with a 50Hz data output rate, a significant signal at 75Hz may alias back into the passband at 25Hz. This is due to the fact that rejection at 75Hz may only be 66dB in the stopband (frequencies higher than the first notch frequency), as shown in Figure 4. However, setting the data output rate to 10Hz will provide 135dB rejection at 75Hz (see Figure 6).
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DIGITAL FILTER RESPONSE 0 –20 –20 –40 –40 –60 –60 –80 Gain (dB) Gain (dB) DIGITAL FILTER RESPONSE 0 –100 –120 –80 –100 –120 –140 –140 –160 –160 –180 –180 –200 –200 0 50 100 150 200 250 0 300 10 20 30 Frequency (Hz) FIGURE 5. Digital Filter Response (60Hz). 60 70 80 90 100 DIGITAL FILTER RESPONSE 0 0 –20 –20 –40 –40 –60 –60 Gain (dB) Gain (dB) 50 FIGURE 6. Digital Filter Response (10Hz Multiples).
PAGE 12
DSYNC The DSYNC signal can be used is two ways. First, DSYNC can be used to synchronize multiple converters. This is done by applying a negative-going pulse on DSYNC. The negative pulse resets the current modulator count to zero and places it in a hold state. The modulator is released from the hold state and synchronization occurs on the rising edge of DSYNC. DSYNC does not reset the internal data to zero. Synchronization assumes that each ADS1250 is driven from the same system clock.
PAGE 13
CS The CS signal controls the state of DOUT. If CS is HIGH, DOUT is in a high-impedance state. When CS is LOW, DOUT drives the bus. MSB to LSB in the time defined by t3. The DRDY line would stay HIGH for the time defined by t4, as shown in Figure 15. t3 DRDY The DRDY signal is used to indicate that new data has been loaded into the data output register and is ready to be read. The operation of DRDY depends on how the CS signal is used.
PAGE 14
There are three basic methods of receiving data from the ADS1250. The first two methods involve a four-wire interface and the third method is a three-wire interface. Method 1: Four-Wire Interface The most common method of receiving data is using a simple four-wire interface (CS, SCLK, DOUT, and DRDY). The DRDY line will pulse LOW after the DOR is updated. The processor would then take CS LOW to select the device for communication.
PAGE 15
Method 2: Four-Wire Interface The second method of receiving data also uses a simple four-wire interface (CS, SCLK, DOUT, and DRDY). The main difference from method 1 is that SCLK is a freerunning clock. The DRDY line will pulse LOW for the time defined by t2 after the DOR is updated. The processor would then take CS LOW to select the device for communication. The recommended method of using CS is to take CS LOW on the falling edge of SCLK.
PAGE 16
Method 3: Three-Wire Interface The third method of receiving data uses a simple three-wire interface (SCLK, DOUT, and DRDY). The main difference from method 1 is that CS is tied LOW, therefore, the DOUT pin is always driving the bus. The DRDY line will pulse LOW after the DOR is updated. Since CS is tied LOW (the DOUT pin is enabled for output), the level dictated by the MSB of the data output register would be driven on the bus. The processor would provide 20 (or 24) SCLKs to read the contents of the DOR.
PAGE 17
DVDD 8xC51 AGND AVDD VREF Circuit +VIN DGND –VIN G1 P0.0 P1.2 P0.1 P1.3 P0.2 DRDY P1.4 P0.3 G0 +VS CS ADS1250 DGND CLK P1.5 P0.4 +VD SCLK P1.6 P0.5 DGND DOUT P1.7 P0.6 RST P0.7 P3.0 EA DSYNC DVDD P1.1 AGND VREF VCC P1.0 / T2 DGND DVDD ALE P3.1 P3.2 / INT0 PSEN P3.3 P2.7 P3.4 P2.6 P3.5 P2.5 P3.6 P2.4 P3.7 P2.3 XTAL2 P2.2 C1 XTAL C2 XTAL1 P2.1 VSS P2.0 DGND FIGURE 22. Five-Wire Interface to an 8xC51.
PAGE 18
SOFTWARE GAIN The excellent performance, flexibility, and low cost of the ADS1250 allows the converter to be considered for designs which would not normally need a 20-bit ADC. For example, many designs utilize a 12-bit converter and a high gain INA or PGA for digitizing low amplitude signals. For some of these applications, the ADS1250 by itself may be a solution.
PAGE 19
LAYOUT should be connected to the analog ground plane as well as all other analog grounds. DGND should be connected to the digital ground plane and all digital signals referenced to this plane. The ADS1250 pinout is such that the converter is cleanly separated into an analog and digital portion. This should allow simple layout of the analog and digital sections of the design. For a single converter system, AGND and DGND of the ADS1250 should be connected together, underneath the converter.
PAGE 20
SYSTEM CONSIDERATIONS analog inputs of the ADS1250 are at 2.048V, the differential voltage is 0V. If one input is at 0V and the other is at 4.096V, the differential voltage magnitude is 4.096V. This is the case regardless of which input is at 0V and which is at 4.096V. The analog input differential voltage is given by the following equation: +VIN – –VIN The recommendations for power supplies and grounding will change depending on the requirements and specific design of the overall system.
PAGE 21
PACKAGE OPTION ADDENDUM www.ti.
PAGE 22
PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device ADS1250U/1K Package Package Pins Type Drawing SOIC DW 16 SPQ Reel Reel Diameter Width (mm) W1 (mm) 1000 330.0 16.4 Pack Materials-Page 1 A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 10.85 10.8 2.7 12.0 16.
PAGE 23
PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS1250U/1K SOIC DW 16 1000 346.0 346.0 33.
PAGE 24
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.