Datasheet
Table Of Contents
- Devices Included in this Data Sheet:
- Microcontroller Core Features:
- Pin Diagram
- Peripheral Features:
- Pin Diagrams
- Table of Contents
- 1.0 Device Overview 5
- 2.0 Memory Organization 11
- 3.0 I/O Ports 29
- 4.0 Data EEPROM and FLASH Program Memory 41
- 5.0 Timer0 Module 47
- 6.0 Timer1 Module 51
- 7.0 Timer2 Module 55
- 8.0 Capture/Compare/PWM Modules 57
- 9.0 Master Synchronous Serial Port (MSSP) Module 65
- 10.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (USART) 95
- 11.0 Analog-to-Digital Converter (A/D) Module 111
- 12.0 Special Features of the CPU 119
- 13.0 Instruction Set Summary 135
- 14.0 Development Support 143
- 15.0 Electrical Characteristics 149
- 16.0 DC and AC Characteristics Graphs and Tables 177
- 17.0 Packaging Information 189
- Most Current Data Sheet
- Errata
- Customer Notification System
- 1.0 Device Overview
- 2.0 Memory Organization
- 3.0 I/O Ports
- 4.0 Data EEPROM and Flash Program Memory
- 4.1 EECON1 and EECON2 Registers
- 4.2 Reading the EEPROM Data Memory
- 4.3 Writing to the EEPROM Data Memory
- 4.4 Reading the FLASH Program Memory
- 4.5 Writing to the FLASH Program Memory
- 4.6 Write Verify
- 4.7 Protection Against Spurious Writes
- 4.8 Operation While Code Protected
- 4.9 FLASH Program Memory Write Protection
- 5.0 Timer0 Module
- 6.0 Timer1 Module
- 6.1 Timer1 Operation in Timer Mode
- 6.2 Timer1 Counter Operation
- 6.3 Timer1 Operation in Synchronized Counter Mode
- 6.4 Timer1 Operation in Asynchronous Counter Mode
- 6.5 Timer1 Oscillator
- 6.6 Resetting Timer1 using a CCP Trigger Output
- 6.7 Resetting of Timer1 Register Pair (TMR1H, TMR1L)
- 6.8 Timer1 Prescaler
- 7.0 Timer2 Module
- 8.0 Capture/Compare/PWM Modules
- 9.0 Master Synchronous Serial Port (MSSP) Module
- 9.1 SPI Mode
- 9.2 MSSP I2C Operation
- 9.2.1 SLAVE Mode
- 9.2.2 General Call Address Support
- 9.2.3 Sleep Operation
- 9.2.4 Effects of a Reset
- 9.2.5 Master Mode
- 9.2.6 Multi-master Mode
- 9.2.7 I2C Master Mode Support
- 9.2.8 Baud Rate Generator
- 9.2.9 I2C Master Mode Start Condition Timing
- 9.2.10 I2C Master Mode Repeated Start Condition Timing
- 9.2.11 I2C Master Mode Transmission
- 9.2.12 I2C Master Mode Reception
- 9.2.13 Acknowledge Sequence Timing
- 9.2.14 Stop Condition Timing
- 9.2.15 Clock Arbitration
- 9.2.16 Sleep Operation
- 9.2.17 Effects of a Reset
- 9.2.18 Multi -Master Communication, Bus Collision, And Bus Arbitration
- 9.3 Connection Considerations for I2C Bus
- 10.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (USART)
- 11.0 Analog-to-Digital Converter (A/D) Module
- 12.0 Special Features of the CPU
- 12.1 Configuration Bits
- 12.2 Oscillator Configurations
- 12.3 RESET
- 12.4 Power-On Reset (POR)
- 12.5 Power-up Timer (PWRT)
- 12.6 Oscillator Start-up Timer (OST)
- 12.7 Brown-out Reset (BOR)
- 12.8 Time-out Sequence
- 12.9 Power Control/Status Register (PCON)
- 12.10 Interrupts
- 12.11 Context Saving During Interrupts
- 12.12 Watchdog Timer (WDT)
- 12.13 Power-down Mode (SLEEP)
- 12.14 In-Circuit Debugger
- 12.15 Program Verification/Code Protection
- 12.16 ID Locations
- 12.17 In-Circuit Serial Programming
- 12.18 Low Voltage ICSP Programming
- 13.0 Instruction Set Summary
- 14.0 Development Support
- 14.1 MPLAB Integrated Development Environment Software
- 14.2 MPASM Assembler
- 14.3 MPLAB C17 and MPLAB C18 C Compilers
- 14.4 MPLINK Object Linker/ MPLIB Object Librarian
- 14.5 MPLAB SIM Software Simulator
- 14.6 MPLAB ICE High Performance Universal In-Circuit Emulator with MPLAB IDE
- 14.7 ICEPIC In-Circuit Emulator
- 14.8 MPLAB ICD In-Circuit Debugger
- 14.9 PRO MATE II Universal Device Programmer
- 14.10 PICSTART Plus Entry Level Development Programmer
- 14.11 PICDEM 1 Low Cost PIC MCU Demonstration Board
- 14.12 PICDEM 2 Low Cost PIC16CXX Demonstration Board
- 14.13 PICDEM 3 Low Cost PIC16CXXX Demonstration Board
- 14.14 PICDEM 17 Demonstration Board
- 14.15 KeeLoq Evaluation and Programming Tools
- 15.0 Electrical Characteristics
- 15.1 DC Characteristics: PIC16F873/874/876/877-04 (Commercial, Industrial) PIC16F873/874/876/877-20 (Commercial, Industrial) PIC16LF873/874/876/877-04 (Commercial, Industrial)
- 15.2 DC Characteristics: PIC16F873/874/876/877-04 (Commercial, Industrial) PIC16F873/874/876/877-20 (Commercial, Industrial) PIC16LF873/874/876/877-04 (Commercial, Industrial)
- 15.3 DC Characteristics: PIC16F873/874/876/877-04 (Extended) PIC16F873/ 874/ 876/ 877-10 (Extended)
- 15.4 DC Characteristics: PIC16F873/874/876/877-04 (Extended) PIC16F873/874/876/877-10 (Extended)
- 15.5 Timing Parameter Symbology
- 16.0 DC and AC Characteristics Graphs and Tables
- 17.0 Packaging Information
- 17.1 Package Marking Information
- Package Marking Information (Cont’d)
- 28-Lead Skinny Plastic Dual In-line (SP) – 300 mil (PDIP)
- 28-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC)
- 40-Lead Plastic Dual In-line (P) – 600 mil (PDIP)
- 44-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)
- 44-Lead Plastic Metric Quad Flatpack (PQ) 10x10x2 mm Body, 1.6/0.15 mm Lead Form (MQFP)
- 44-Lead Plastic Leaded Chip Carrier (L) – Square (PLCC)
- Appendix A: Revision History
- Appendix B: Device Differences
- Appendix C: Conversion CONSIDERATIONS
- Index
- A
- Acquisition Requirements 114
- ADCON0 Register 111
- ADCON1 Register 112
- ADIF bit 112
- Analog Input Model Block Diagram 114
- Analog Port Pins 7, 8, 9, 36, 38
- Associated Registers and Bits 117
- Block Diagram 113
- Calculating Acquisition Time 114
- Configuring Analog Port Pins 115
- Configuring the Interrupt 113
- Configuring the Module 113
- Conversion Clock 115
- Conversions 116
- Delays 114
- Effects of a RESET 117
- GO/DONE bit 112
- Internal Sampling Switch (Rss) Impedence 114
- Operation During SLEEP 117
- Result Registers 116
- Sampling Requirements 114
- Source Impedence 114
- Time Delays 114
- AN552 (Implementing Wake-up on Key Strokes Using PIC16CXXX) 31
- AN556 (Implementing a Table Read) 26
- AN578 (Use of the SSP Module in the I2C Multi-Master Environment) 73
- PIC16F873/PIC16F876 Block Diagram 5
- PIC16F874/PIC16F877 Block Diagram 6
- MPASM Assembler 143
- A/D 113
- A/D Converter 113
- Analog Input Model 114
- Baud Rate Generator 79
- Capture Mode 59
- Compare Mode 60
- I2C Master Mode 78
- I2C Module 73
- I2C Slave Mode 73
- Interrupt Logic 129
- PIC16F873/PIC16F876 5
- PIC16F874/PIC16F877 6
- PORTA
- PORTB
- PORTC
- PORTD 35
- PORTD and PORTE (Parallel Slave Port) 38
- PORTE 36
- PWM Mode 61
- RESET Circuit 123
- SSP (I2C Mode) 73
- SSP (SPI Mode) 69
- Timer0/WDT Prescaler 47
- Timer1 52
- Timer2 55
- USART Asynchronous Receive 101
- USART Asynchronous Receive (9-bit Mode) 103
- USART Transmit 99
- Watchdog Timer 131
- BOR Status (BOR Bit) 25
- Associated Registers
- Capture Mode 59
- CCP Timer Resources 57
- CCP1
- CCP2
- Compare
- Compare Mode 60
- Interaction of Two CCP Modules (table) 57
- PWM Mode 61
- Special Event Trigger and A/D Conversions 60
- Call of a Subroutine in Page 1 from Page 0 26
- EEPROM Data Read 43
- EEPROM Data Write 43
- FLASH Program Read 44
- FLASH Program Write 45
- Indirect Addressing 27
- Initializing PORTA 29
- Saving STATUS, W and PCLATH Registers 130
- Data EEPROM and FLASH Program Memory 45
- Associated Registers 46
- Code Protection 45
- Reading 43
- Special Functions Registers 41
- Spurious Write Protection 45
- Write Verify 45
- Writing to 43
- Bank Select (RP1:RP0 Bits) 12, 18
- General Purpose Registers 12
- Register File Map 13, 14
- Special Function Registers 15
- Commercial and Industrial 152– 156
- Extended 157– 160
- Associated Registers 46
- Code Protection 45
- Configuration Bits and Read/Write State 46
- Reading 44
- Special Function Registers 41
- Spurious Write Protection 45
- Write Protection 46
- Write Verify 45
- Writing to 44
- Connection Considerations 94
- Sample Device Configuration 94
- Acknowledge Sequence Timing 86
- Addressing 74
- Associated Registers 77
- Baud Rate Generator 79
- Block Diagram 78
- BRG Block Diagram 79
- BRG Reset due to SDA Collision 91
- BRG Timing 80
- Bus Arbitration 89
- Bus Collision 89
- Bus Collision Timing 89
- Clock Arbitration 88
- Clock Arbitration Timing (Master Transmit) 88
- Conditions to not give ACK Pulse 74
- General Call Address Support 76
- Master Mode 78
- Master Mode 7-bit Reception Timing 85
- Master Mode Block Diagram 78
- Master Mode Operation 79
- Master Mode START Condition 80
- Master Mode Transmission 82
- Master Mode Transmit Sequence 79
- Multi-Master Communication 89
- Multi-master Mode 78
- Operation 73
- Repeat START Condition Timing 81
- Slave Mode 74
- Slave Reception 74
- Slave Transmission 75
- SSPBUF 73
- STOP Condition Receive or Transmit Timing 87
- STOP Condition Timing 87
- Waveforms for 7-bit Reception 75
- Waveforms for 7-bit Transmission 76
- FSR Register 12
- ADDLW 137
- ADDWF 137
- ANDLW 137
- ANDWF 137
- BCF 137
- BSF 137
- BTFSC 137
- BTFSS 137
- CALL 138
- CLRF 138
- CLRW 138
- CLRWDT 138
- COMF 138
- DECF 138
- DECFSZ 139
- GOTO 139
- INCF 139
- INCFSZ 139
- IORLW 139
- IORWF 139
- MOVF 140
- MOVLW 140
- MOVWF 140
- NOP 140
- RETFIE 140
- RETLW 140
- RETURN 141
- RLF 141
- RRF 141
- SLEEP 141
- SUBLW 141
- SUBWF 141
- SWAPF 142
- XORLW 142
- XORWF 142
- Summary Table 136
- GIE Bit 20
- INTE Bit 20
- INTF Bit 20
- PEIE Bit 20
- RBIE Bit 20
- RBIF Bit 20, 31
- T0IE Bit 20
- T0IF Bit 20
- Block Diagram 129
- Interrupt-on-Change (RB7:RB4 ) 31
- RB0/INT Pin, External 7, 8, 130
- TMR0 Overflow 130
- USART Receive/Transmit Complete 95
- Bus Collision Interrupt 24
- Synchronous Serial Port Interrupt 22
- Global Interrupt Enable (GIE Bit) 20, 129
- Interrupt-on-Change (RB7:RB4) Enable (RBIE Bit) 130
- Interrupt-on-Change (RB7:RB4) Enable (RBIE Bit) 20
- Peripheral Interrupt Enable (PEIE Bit) 20
- RB0/INT Enable (INTE Bit) 20
- TMR0 Overflow Enable (T0IE Bit) 20
- Interrupt-on-Change (RB7:RB4) Flag (RBIF Bit) 130
- Interrupt-on-Change (RB7:RB4) Flag (RBIF Bit) 20, 31
- RB0/INT Flag (INTF Bit) 20
- TMR0 Overflow Flag (T0IF Bit) 20, 130
- MCLR Reset, Normal Operation 123, 125, 126
- MCLR Reset, SLEEP 123, 125, 126
- Data Memory 12
- Program Memory 11
- INTEDG Bit 19
- PS2:PS0 Bits 19
- PSA Bit 19
- T0CS Bit 19
- T0SE Bit 19
- HS 121, 124
- LP 121, 124
- RC 121, 122, 124
- XT 121, 124
- Capacitor Selection 122
- Crystal and Ceramic Resonators 121
- RC 122
- Associated Registers 39
- Block Diagram 38
- RE0/RD/AN5 Pin 9, 36, 38
- RE1/WR/AN6 Pin 9, 36, 38
- RE2/CS/AN7 Pin 9, 36, 38
- Read Waveforms 39
- Select (PSPMODE Bit) 35, 36, 37, 38
- Write Waveforms 39
- BOR Bit 25
- POR Bit 25
- PIC16F873/PIC16F876 7
- PIC16F874/PIC16F877 8
- Analog Port Pins 7, 8
- Associated Registers 30
- Block Diagram
- Initialization 29
- PORTA Register 15, 29
- RA3
- RA4/T0CKI Pin 7, 8
- RA5/SS/AN4 Pin 7, 8
- TRISA Register 29
- Associated Registers 32
- Block Diagram
- PORTB Register 15, 31
- RB0/INT Edge Select (INTEDG Bit) 19
- RB0/INT Pin, External 7, 8, 130
- RB7:RB4 Interrupt on Change 130
- RB7:RB4 Interrupt on Change Enable (RBIE Bit) 130
- RB7:RB4 Interrupt on Change Flag (RBIF Bit) 130
- RB7:RB4 Interrupt-on-Change Enable (RBIE Bit) 20
- RB7:RB4 Interrupt-on-Change Flag (RBIF Bit) 20, 31
- TRISB Register 17, 31
- Associated Registers 34
- Block Diagrams
- PORTC Register 15, 33
- RC0/T1OSO/T1CKI Pin 7, 9
- RC1/T1OSI/CCP2 Pin 7, 9
- RC2/CCP1 Pin 7, 9
- RC3/SCK/SCL Pin 7, 9
- RC4/SDI/SDA Pin 7, 9
- RC5/SDO Pin 7, 9
- RC6/TX/CK Pin 7, 9, 96
- RC7/RX/DT Pin 7, 9, 96, 97
- TRISC Register 33, 95
- Associated Registers 35
- Block Diagram 35
- Parallel Slave Port (PSP) Function 35
- PORTD Register 15, 35
- TRISD Register 35
- Analog Port Pins 9, 36, 38
- Associated Registers 36
- Block Diagram 36
- Input Buffer Full Status (IBF Bit) 37
- Input Buffer Overflow (IBOV Bit) 37
- Output Buffer Full Status (OBF Bit) 37
- PORTE Register 15, 36
- PSP Mode Select (PSPMODE Bit) 35, 36, 37, 38
- RE0/RD/AN5 Pin 9, 36, 38
- RE1/WR/AN6 Pin 9, 36, 38
- RE2/CS/AN7 Pin 9, 36, 38
- TRISE Register 36
- Assignment (PSA Bit) 19
- Rate Select (PS2:PS0 Bits) 19
- Oscillator Start-up Timer (OST) 119, 124
- POR Status (POR Bit) 25
- Power Control (PCON) Register 124
- Power-down (PD Bit) 18, 123
- Power-up Timer (PWRT) 119, 124
- Time-out (TO Bit) 18, 123
- Time-out Sequence on Power-up 127, 128
- Assignment (PSA Bit) 19
- Rate Select (PS2:PS0 Bits) 19
- RESET Conditions 125
- Interrupt Vector 11
- Paging 11, 26
- Program Memory Map 11
- RESET Vector 11
- ADDEN Bit 96
- CREN Bit 96
- FERR Bit 96
- OERR Bit 96
- RX9 Bit 96
- RX9D Bit 96
- SPEN Bit 95, 96
- SREN Bit 96
- ADCON0 (A/D Control 0) 111
- ADCON1 (A/D Control 1) 112
- CCP1CON (CCP Control 1) 58
- EECON2 41
- FSR 27
- INTCON 20
- OPTION_REG 19, 48
- PCON (Power Control) 25
- PIE1 (Peripheral Interrupt Enable 1) 21
- PIE2 (Peripheral Interrupt Enable 2) 23
- PIR1 (Peripheral Interrupt Request 1) 22
- PIR2 (Peripheral Interrupt Request 2) 24
- RCSTA (Receive Status and Control) 96
- Special Function, Summary 15
- SSPCON2 (Sync Serial Port Control 2) 68
- STATUS 18
- T1CON (Timer1 Control) 51
- T2CON (Timer 2 Control)
- TRISE 37
- TXSTA (Transmit Status and Control) 95
- Block Diagram 123
- MCLR Reset. See MCLR
- Brown-out Reset (BOR). See Brown-out Reset (BOR)
- Power-on Reset (POR). See Power-on Reset (POR)
- RESET Conditions for PCON Register 125
- RESET Conditions for Program Counter 125
- RESET Conditions for STATUS Register 125
- WDT Reset. See Watchdog Timer (WDT)
- Data EEPROM and FLASH Program Memory 41
- Master Mode 70
- Master Mode Timing 70
- Serial Clock 69
- Serial Data In 69
- Serial Data Out 69
- Serial Peripheral Interface (SPI) 65
- Slave Mode Timing 71
- Slave Mode Timing Diagram 71
- Slave Select 69
- SPI Clock 70
- SPI Mode 69
- Associated Registers 72
- Slave Mode 71
- Block Diagram (SPI Mode) 69
- RA5/SS/AN4 Pin 7, 8
- RC3/SCK/SCL Pin 7, 9
- RC4/SDI/SDA Pin 7, 9
- RC5/SDO Pin 7, 9
- SPI Mode 69
- SSPADD 73, 74
- SSPBUF 70, 73
- SSPCON2 68
- SSPSR 70, 74
- SSPSTAT 73
- SSP I2C Operation 73
- SPI Master Mode 70
- SPI Slave Mode 71
- SSPCON1 Register 73
- Overflows 26
- Underflow 26
- C Bit 18
- DC Bit 18
- IRP Bit 18
- PD Bit 18, 123
- RP1:RP0 Bits 18
- TO Bit 18, 123
- Z Bit 18
- Associated Registers 49
- Clock Source Edge Select (T0SE Bit) 19
- Clock Source Select (T0CS Bit) 19
- External Clock 48
- Interrupt 47
- Overflow Enable (T0IE Bit) 20
- Overflow Flag (T0IF Bit) 20, 130
- Overflow Interrupt 130
- Prescaler 48
- RA4/T0CKI Pin, External Clock 7, 8
- T0CKI 48
- WDT Prescaler Block Diagram 47
- Associated Registers 54
- Asynchronous Counter Mode 53
- Block Diagram 52
- Counter Operation 52
- Operation in Timer Mode 52
- Oscillator 53
- Prescaler 54
- RC0/T1OSO/T1CKI Pin 7, 9
- RC1/T1OSI/CCP2 Pin 7, 9
- Resetting of Timer1 Registers 54
- Resetting Timer1 using a CCP Trigger Output 53
- Synchronized Counter Mode 52
- T1CON 51
- T1CON Register 51
- TMR1H 53
- TMR1L 53
- Associated Registers 56
- Block Diagram 55
- Output 56
- Postscaler 55
- Prescaler 55
- T2CON 55
- A/D Conversion 175
- Acknowledge Sequence Timing 86
- Baud Rate Generator with Clock Arbitration 80
- BRG Reset Due to SDA Collision 91
- Brown-out Reset 164
- Bus Collision
- Bus Collision During a Repeated START Condition (Case 1) 92
- Bus Collision During a Repeated START Condition (Case2) 92
- Bus Collision During a START Condition (SCL = 0) 91
- Bus Collision During a STOP Condition 93
- Bus Collision for Transmit and Acknowledge 89
- Capture/Compare/PWM 166
- CLKOUT and I/O 163
- I2C Bus Data 171
- I2C Bus START/STOP bits 170
- I2C Master Mode First START Bit Timing 80
- I2C Master Mode Reception Timing 85
- I2C Master Mode Transmission Timing 83
- Master Mode Transmit Clock Arbitration 88
- Power-up Timer 164
- Repeat START Condition 81
- RESET 164
- SPI Master Mode 70
- SPI Slave Mode (CKE = 1) 71
- SPI Slave Mode Timing (CKE = 0) 71
- Start-up Timer 164
- STOP Condition Receive or Transmit 87
- Time-out Sequence on Power-up 127, 128
- Timer0 165
- Timer1 165
- USART Asynchronous Master Transmission 100
- USART Asynchronous Reception 102
- USART Synchronous Receive 173
- USART Synchronous Reception 108
- USART Synchronous Transmission 106, 173
- USART, Asynchronous Reception 104
- Wake-up from SLEEP via Interrupt 133
- Watchdog Timer 164
- IBF Bit 37
- IBOV Bit 37
- OBF Bit 37
- PSPMODE Bit 35, 36, 37, 38
- BRGH Bit 95
- CSRC Bit 95
- SYNC Bit 95
- TRMT Bit 95
- TX9 Bit 95
- TX9D Bit 95
- TXEN Bit 95
- Address Detect Enable (ADDEN Bit) 96
- Asynchronous Mode 99
- Asynchronous Receive 101
- Asynchronous Receive (9-bit Mode) 103
- Asynchronous Receive with Address Detect. SeeAsynchronous Receive (9-bit Mode).
- Asynchronous Reception 102
- Asynchronous Transmitter 99
- Baud Rate Generator (BRG) 97
- Clock Source Select (CSRC Bit) 95
- Continuous Receive Enable (CREN Bit) 96
- Framing Error (FERR Bit) 96
- Mode Select (SYNC Bit) 95
- Overrun Error (OERR Bit) 96
- RC6/TX/CK Pin 7, 9
- RC7/RX/DT Pin 7, 9
- RCSTA Register 96
- Receive Data, 9th bit (RX9D Bit) 96
- Receive Enable, 9-bit (RX9 Bit) 96
- Serial Port Enable (SPEN Bit) 95, 96
- Single Receive Enable (SREN Bit) 96
- Synchronous Master Mode 105
- Synchronous Master Reception 107
- Synchronous Master Transmission 105
- Synchronous Slave Mode 108
- Synchronous Slave Reception 109
- Synchronous Slave Transmit 108
- Transmit Block Diagram 99
- Transmit Data, 9th Bit (TX9D) 95
- Transmit Enable (TXEN Bit) 95
- Transmit Enable, Nine-bit (TX9 Bit) 95
- Transmit Shift Register Status (TRMT Bit) 95
- TXSTA Register 95
- Interrupts 125, 126
- MCLR Reset 126
- Timing Diagram 133
- WDT Reset 126
- Block Diagram 131
- Enable (WDTE Bit) 131
- Postscaler. See Postscaler, WDT
- Programming Considerations 131
- RC Oscillator 131
- Time-out Period 131
- WDT Reset, Normal Operation 123, 125, 126
- WDT Reset, SLEEP 123, 125, 126
- Data EEPROM and FLASH Program Memory 45
- On-Line Support
- Reader Response
- PIC16F87X Product Identification System
- To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
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PIC16F87X
DS30292D-page 94 1998-2013 Microchip Technology Inc.
9.3 Connection Considerations for
I
2
C Bus
For standard-mode I
2
C bus devices, the values of
resistors R
p
and R
s
in Figure 9-27 depend on the fol-
lowing parameters:
• Supply voltage
• Bus capacitance
• Number of connected devices
(input current + leakage current)
The supply voltage limits the minimum value of resistor
R
p
,
due to the specified minimum sink current of 3 mA at
V
OL max = 0.4V, for the specified output stages.
For
example, with a supply voltage of V
DD = 5V±10% and
V
OL max = 0.4V at 3 mA, R
p
min = (5.5-0.4)/0.003 = 1.7 k
V
DD as a function of R
p
is shown in Figure 9-27. The
desired noise margin of 0.1V
DD for the low level limits
the maximum value of R
s
. Series resistors are optional
and used to improve ESD susceptibility.
The bus capacitance is the total capacitance of wire,
connections, and pins. This capacitance limits the max-
imum value of R
p
due to the specified rise time
(Figure 9-27).
The SMP bit is the slew rate control enabled bit. This bit
is in the SSPSTAT register, and controls the slew rate
of the I/O pins when in I
2
C mode (master or slave).
FIGURE 9-27: SAMPLE DEVICE CONFIGURATION FOR I
2
C BUS
R
p
R
p
VDD + 10%
SDA
SCL
DEVICE
C
b
=10 - 400 pF
R
s
R
s
Note: I
2
C devices with input levels related to VDD must have one common supply line to which the pull-up resistor is also
connected.