Instruction Manual

_________________________________________________________________________________________________________ 14-10
MAXQ7667 User’s Guide
14.4 Voltage References
The voltage reference for the SAR ADC can either be an internal bandgap reference or an external reference. The internal, 2.5V
bandgap reference can be activated by setting the BGE bit (APE.12) and the RBUFE bit (APE.14) to 1. The BGE bit enables the
bandgap reference, while the RBUFE bit (APE.14) enables the buffer at the output of the bandgap. A bypass capacitor of 0.47µF
should be placed between REFBG and AGND pin.
To provide the reference from an external source, the bandgap buffer must be turned off by setting RBUFE bit (APE.14) to 0, and an
external reference voltage between 1V and AVDD can be connected to the REF pin. A bypass capacitor of 0.47µF should be placed
between REF and AGND pin.
14.5 Analog-to-Digital Converter (ADC) Port
The MAXQ7667 contains a low-power, high-precision, 12-bit, 125ksps successive approximation ADC and five single-ended or two dif-
ferential input channel multiplexer.
14.5.1 Single-Ended/Differential Inputs
The MAXQ7667 ADC uses a fully differential SAR conversion technique and an on-chip track-and-hold (T/H) block to convert voltage
signals into a 12-bit digital result. Both single-ended and differential configurations are supported using an analog input channel mul-
tiplexer that supports five single-ended or two differential channels.
In single-ended mode, the positive analog input (AIN+) for the ADC is connected to the selected input channel and the negative input
(AIN-) is connected to AGND. In differential input configuration, analog inputs AIN+ and AIN- are selected from the following pairs:
AIN0/AIN1, AIN2/AIN3. The differential input configuration references all input signals to the complementary multiplexer channel input,
eliminating common-mode DC offsets and noise. The analog inputs can be configured for either single-ended or differential conver-
sion by writing to the SARDIF (SARC.8) control bit, while analog input channel selection is controlled by the SARMX[2:0] (SARC.11:9)
control field in the SARC peripheral register.
14.5.2 True Differential Analog Input T/H
The equivalent input circuit of the MAXQ7667’s analog input architecture is shown in Figure 14-2 and Figure 14-3. In track (acquisition)
mode, a positive input capacitor is connected to AIN0–AIN4 in single-ended mode or AIN0, AIN2 in differential mode. A negative input
capacitor is connected to AGND in single-ended mode or AIN1, AIN3 in differential mode. T/H timing is controlled by the ADC source
select (SARS[2:0]) and ADC dual mode select SARDUL (SARC.6). SARS[2:0] selects an ADC conversion start source, which could be
one of the timers, ADC conversion pin, or software writes to the ADC start bit. All three conversion start sources support single-edge
or dual-edge modes of operation, which is determined by the SARDUL bit. When SARDUL is set to 1, the ADC operates in dual-edge
mode. The rising edge of the selected conversion start source causes the ADC to power-up and begin acquisition; the falling edge
causes it to sample and perform a conversion. When SARDUL is 0, the ADC operates in single-edge mode. The rising edge controls
the entire conversion, i.e., power-up, acquisition, and conversion sequence if the ADC was off; if the ADC was on, the falling edge
starts the acquisition and then starts conversion. Once a conversion has been initiated, the T/H enters acquisition mode for the next
conversion on the 13th falling edge of ADCCLK, if auto shutdown (SARASD = 0 in the SARC register) is disabled. See
Section 14.5.8:
ADC Conversion Start Sources and Timing for details.
The time required for the T/H to acquire an input signal is determined by how quickly its input capacitance is charged. If the input sig-
nal’s source impedance is high, the acquisition time lengthens. The acquisition time, t
ACQ
, is the minimum time needed for the signal
to be acquired. It is calculated by the following equation:
t
ACQ
≥ k x (R
SOURCE
+ R
IN
) x C
IN
where
k = 9 ≈ ln (2 x 2
12
)
The constant, k, is the number of RC time constants required so that the voltage on the internal sampling capacitor reaches 12-bit
accuracy, i.e., so that the difference between the input voltage and the sampling capacitor voltage is equal to 0.5 LSB.
R
SOURCE
is the source impedance of the input signal. R
IN
= 800Ω is the equivalent differential analog input resistance, and C
IN
= 14pF
is the equivalent differential analog input capacitance. t
ACQ
is never less than 1.5µs (three ADCCLK periods at 2MHz), and any source
impedance less than 4kΩ does not significantly affect the ADC’s AC performance. For higher source impedance, a longer acquisition
time is required.