Datasheet

MAX9209/MAX9213
Programmable DC-Balanced
21-Bit Serializers
12 ______________________________________________________________________________________
AC-Coupling Benefits
Bit errors experienced with DC-coupling can be elimi-
nated by increasing the receiver common-mode volt-
age range by AC-coupling. AC-coupling increases the
common-mode voltage range of an LVDS receiver to
nearly the voltage rating of the capacitor. The typical
LVDS driver output is 350mV centered on an offset volt-
age of 1.25V, making single-ended output voltages of
1.425V and 1.075V. An LVDS receiver accepts signals
from 0V to 2.4V, allowing approximately ±1V common-
mode difference between the driver and receiver on a
DC-coupled link (2.4V - 1.425V = 0.975V and 1.075V -
0V = 1.075V). Figure 13 shows the DC-coupled link,
non-DC-balanced mode.
TxIN1
TxIN7TxIN8
TxIN14TxIN15
CYCLE N + 1CYCLE NCYCLE N - 1
TxIN2TxIN6 TxIN3TxIN4TxIN5
TxIN9TxIN13 TxIN10TxIN11TxIN12
TxIN0TxIN1TxIN2TxIN6 TxIN3TxIN4TxIN5
TxIN7TxIN8TxIN9TxIN13 TxIN10TxIN11TxIN12
TxIN14TxIN15TxIN16TxIN20 TxIN17TxIN18TxIN19
TxIN0TxIN1
TxIN7TxIN8
TxIN14TxIN15TxIN16TxIN20 TxIN17TxIN18TxIN19
TxCLK OUT+
TxIN0
TxCLK OUT-
TxOUT1
TxOUT0
TxOUT2
Figure 12. Non-DC-Balanced Mode Inputs Mapped to LVDS Outputs
1:7
7
7
R
T
=
100Ω
R
T
=
100Ω
R
T
=
100Ω
R
T
=
100Ω
7:1
7:1
1:7
7
7
7:1
1:7
7
7
PLL
PLL
MAX9209
MAX9213
MAX9210
MAX9214
TxOUT
TxCLK OUT
RxIN
RxCLK IN
21:3 SERIALIZER 3:21 DESERIALIZER
PWRDWN
RxCLK OUT
RxOUT
PWRDWN
TxCLK IN
TxIN
TRANSMISSION LINE
R
O
R
O
R
O
R
O
Figure 13. DC-Coupled Link, Non-DC-Balanced Mode