Datasheet

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General Description

The MAX9209/MAX9213 serialize 21 bits of LVTTL/

LVCMOS parallel input data to three LVDS outputs. A

parallel rate clock on a fourth LVDS output provides

timing for deserialization.

The MAX9209/MAX9213 feature programmable DC bal-

ance, which allows isolation between the serializer and

deserializer using AC-coupling. The DC balance circuits

on each channel code the data, limiting the imbalance

of transmitted ones and zeros to a defined range. The

companion MAX9210/MAX9214 deserializers decode

the data. When DC balance is not programmed, the

serializers are compatible with non-DC-balanced, 21-bit

serializers such as the DS90CR215 and DS90CR217.

Two frequency ranges and two DC-balance default

conditions are available for maximum replacement flexi-

bility and compatibility with existing non-DC-balanced

serializers.

The MAX9209/MAX9213 are available in TSSOP and

space-saving TQFN packages.

Applications

Automotive Navigation Systems

Automotive DVD Entertainment Systems

Digital Copiers

Laser Printers

Features

o Programmable DC-Balanced or Non-DC-Balanced

Operation

o DC Balance Allows AC-Coupling for Ground-Shift

Tolerance

o As Low as 8MHz Operation

o Pin Compatible with DS90CR215 and DS90CR217

in Non-DC-Balanced Mode

o Integrated 110Ω (DC-Balanced) and 410Ω (Non-

DC-Balanced) Output Resistors

o 5V Tolerant LVTTL/LVCMOS Data Inputs

o PLL Requires No External Components

o Up to 1.785Gbps Throughput

o LVDS Outputs Meet IEC 61000-4-2 and ISO 10605

Requirements

o LVDS Outputs Conform to ANSI TIA/EIA-644

LVDS Standard

o Low-Profile 48-Lead TSSOP and Space-Saving

TQFN Packages

o -40°C to +85°C Operating Temperature Range

o +3.3V Supply

MAX9209/MAX9213

Programmable DC-Balanced

21-Bit Serializers

________________________________________________________________

Maxim Integrated Products

Ordering Information

19-2828; Rev 5; 3/12

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,

or visit Maxim’s website at www.maxim-ic.com.

Denotes a lead(Pb)-free/RoHS-compliant package.

/V denotes an automotive qualified part.

*EP = Exposed pad.

EVALUATION KIT

AVAILABLE

PART TEMP. RANGE PIN-PACKAGE

MAX9209EUM+

-40°C to +85°C 48 TSSOP

MAX9209EUM/V+

-40°C to +85°C 48 TSSOP

MAX9209GUM+

-40°C to +105°C 48 TSSOP

MAX9213ETM+ -40°C to +85°C 48 TQFN-EP*

MAX9213EUM+ -40°C to +85°C 48 TSSOP

Pin Configurations appear at end of data sheet.

TxIN 0 - 20 21

TIMING

CONTROL

PARALLEL-TO-

SERIAL

CONVERTER

AND

DC-BALANCE

LOGIC

CLOCK

GENERATOR

PLL

7X OR 9X

LVDS DRIVER 0

LVDS DRIVER 1

LVDS DRIVER 2

LVDS CLK

TxOUT0+

TxOUT0-

TxOUT1+

TxOUT1-

TxOUT2+

TxOUT2-

TxCLK OUT+

TxCLK OUT-

DCB/NC

TxCLK IN

MAX9209

MAX9213

Functional Diagram

Summary of content (18 pages)

PAGE 1
9-2828; Rev 5; 3/12 KIT ATION EVALU E L B A IL AVA Programmable DC-Balanced 21-Bit Serializers Features The MAX9209/MAX9213 serialize 21 bits of LVTTL/ LVCMOS parallel input data to three LVDS outputs. A parallel rate clock on a fourth LVDS output provides timing for deserialization. The MAX9209/MAX9213 feature programmable DC balance, which allows isolation between the serializer and deserializer using AC-coupling.
PAGE 2
MAX9209/MAX9213 Programmable DC-Balanced 21-Bit Serializers ABSOLUTE MAXIMUM RATINGS VCC to GND ...........................................................-0.5V to +4.0V LVDS Outputs (TxOUT_, TxCLK OUT_) to GND ...-0.5V to +4.0V 5V Tolerant LVTTL/LVCMOS Inputs (TxIN_, TxCLK IN, PWRDWN) to GND ..............-0.5V to +6.0V (DCB/NC) to GND ......................................-0.5V to (VCC + 0.5V) LVDS Outputs (TxOUT_, TxCLK OUT_) Short to GND and Differential Short .......................
PAGE 3
Programmable DC-Balanced 21-Bit Serializers (VCC = +3.0V to +3.6V, RL = 100Ω ±1%, PWRDWN = high, DCB/NC = high or low, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25°C.) (Notes 1, 2) PARAMETER Output High-Impedance Current SYMBOL IOZ CONDITIONS DC-balanced mode, worst-case pattern, CL = 5pF, Figure 2 Worst-Case Supply Current ICCW Non-DC-balanced mode, worst-case pattern, CL = 5pF, Figure 2 Power-Down Supply Current ICCZ MIN TYP MAX UNITS -0.5 ±0.1 +0.
PAGE 4
MAX9209/MAX9213 Programmable DC-Balanced 21-Bit Serializers AC ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, RL = 100Ω ±1%, CL = 5pF, PWRDWN = high, DCB/NC = high or low, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25°C.
PAGE 5
Programmable DC-Balanced 21-Bit Serializers (VCC = +3.0V to +3.6V, RL = 100Ω ±1%, CL = 5pF, PWRDWN = high, DCB/NC = high or low, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25°C.) (Notes 4, 5) PARAMETER TxCLK IN High Time SYMBOL TCIH Figure 7 MIN 0.3 x TCIP TCIL Figure 7 0.3 x TCIP TxCLK IN Low Time CONDITIONS TYP MAX UNITS 0.7 x TCIP ns 0.7 x TCIP ns TxIN to TxCLK IN Setup TSTC Figure 7 2.
PAGE 6
Typical Operating Characteristics (continued) (VCC = +3.3V, RL = 100Ω ±1%, CL = 5pF, PWRDWN = high, TA = +25°C, unless otherwise noted.
PAGE 7
Programmable DC-Balanced 21-Bit Serializers PIN TSSOP TQFN 1, 3, 4, 44, 45, 47, 48, 38, 39, 41, 42, 43, 45, 46 NAME TxIN0–TxIN6 FUNCTION 5V Tolerant LVTTL/LVCMOS Channel 0 Data Inputs. Internally pulled down to GND. 2, 8, 14, 21 2, 8, 15, 44 VCC Digital Supply Voltage 5, 11, 17, 24, 46 5, 11, 18, 40, 47 GND Ground 6, 7, 9, 10, 12, 13, 15 1, 3, 4, 6, 7, 9, 48 TxIN7–TxIN13 5V Tolerant LVTTL/LVCMOS Channel 1 Data Inputs. Internally pulled down to GND.
PAGE 8
MAX9209/MAX9213 Programmable DC-Balanced 21-Bit Serializers TxOUT_- OR TxCLK OUT- VOS(-) VOS(+) VOS(-) TxOUT_+ OR TxCLK OUT+ ∆VOS = |VOS(+) - VOS(-)| VOD(+) 0V ∆VOD = |VOD(+) - VOD(-)| VOD(-) VOD(-) (TxOUT_+) - (TxOUT_-) OR (TxCLK OUT+) - (TxCLK OUT-) Figure 1. LVDS Output DC Parameters TCIP TxCLK IN ODD TxIN EVEN TxIN Figure 2.
PAGE 9
Programmable DC-Balanced 21-Bit Serializers MAX9209/MAX9213 TxCLK OUT (DIFFERENTIAL) CYCLE N - 1 CYCLE N TxOUT2 (SINGLE ENDED) TxIN15 TxIN14 TxIN20 TxIN19 TxIN18 TxIN17 TxIN16 TxIN15 TxIN14 TxOUT1 (SINGLE ENDED) TxIN8 TxIN7 TxIN13 TxIN12 TxIN11 TxIN10 TxIN9 TxIN8 TxIN7 TxOUT0 (SINGLE ENDED) TxIN1 TxIN0 TxIN6 TxIN5 TxIN4 TxIN3 TxIN2 TxIN1 TxIN0 TPPos0 TPPos1 TPPos2 TPPos3 TPPos4 TPPos5 TPPos6 Figure 5.
PAGE 10
MAX9209/MAX9213 Programmable DC-Balanced 21-Bit Serializers TxCLK OUT (DIFFERENTIAL) CYCLE N - 1 CYCLE N TxOUT2 (SINGLE ENDED) DCA2 DCB2 TxIN20 TxIN19 TxIN18 TxIN17 TxIN16 TxIN15 TxIN14 DCA2 DCB2 TxOUT1 (SINGLE ENDED) DCA1 DCB1 TxIN13 TxIN12 TxIN11 TxIN10 TxIN9 TxIN8 TxIN7 DCA1 DCB1 TxOUT0 (SINGLE ENDED) DCA0 DCB0 TxIN6 TxIN5 TxIN4 TxIN3 TxIN2 TxIN1 TxIN0 DCA0 DCB0 TPPos0 TPPos1 TPPos2 TPPos3 TPPos4 TPPos5 TPPos6 TPPos7 TPPos8 Figure 6.
PAGE 11
Programmable DC-Balanced 21-Bit Serializers MAX9209/MAX9213 2.0V PWRDWN 3.6V 3.0V VCC TPPLS TxCLK IN TxOUT_, TxCLK OUT VOD = 0 HIGH-Z DIFFERENTIAL 0 Figure 9. PLL Set Time PWRDWN 0.8V TxCLK IN TPDD TxOUT_, TxCLK OUT HIGH-Z Figure 10.
PAGE 12
MAX9209/MAX9213 Programmable DC-Balanced 21-Bit Serializers TxCLK OUT+ TxCLK OUTCYCLE N - 1 TxIN15 CYCLE N CYCLE N + 1 TxIN14 TxIN20 TxIN19 TxIN18 TxIN17 TxIN16 TxIN15 TxIN14 TxIN20 TxIN19 TxIN18 TxIN17 TxIN16 TxIN15 TxIN14 TxIN7 TxIN13 TxIN12 TxIN11 TxIN10 TxIN9 TxIN8 TxIN7 TxIN13 TxIN12 TxIN11 TxIN10 TxIN9 TxIN8 TxIN7 TxIN0 TxIN6 TxIN5 TxIN4 TxIN3 TxIN2 TxIN1 TxIN0 TxIN6 TxIN5 TxIN4 TxIN3 TxIN2 TxIN1 TxIN0 TxOUT2 TxIN8 TxOUT1 TxIN1 TxOUT0 Figure 12.
PAGE 13
Programmable DC-Balanced 21-Bit Serializers TxOUT MAX9210 MAX9214 RxIN 7 7 (7 + 2):1 RO RT = 100Ω 1:(9 - 2) (7 + 2):1 RO RT = 100Ω 1:(9 - 2) (7 + 2):1 RO RT = 100Ω 1:(9 - 2) PLL RO RT = 100Ω PLL 7 TxIN MAX9209/MAX9213 MAX9209 MAX9213 HIGH-FREQUENCY CERAMIC SURFACE-MOUNT CAPACITORS CAN ALSO BE PLACED AT SERIALIZER INSTEAD OF DESERIALIZER. 7 PWRDWN TxCLK IN TxCLK OUT 7 RxOUT 7 PWRDWN RxCLK OUT RxCLK IN 21:3 SERIALIZER 3:21 DESERIALIZER Figure 14.
PAGE 14
MAX9209/MAX9213 Programmable DC-Balanced 21-Bit Serializers HIGH-FREQUENCY CERAMIC SURFACE-MOUNT CAPACITORS MAX9209 MAX9213 MAX9210 MAX9214 TxOUT RxIN 7 RO RT = 100Ω 1:(9 - 2) (7 + 2):1 RO RT = 100Ω 1:(9 - 2) (7 + 2):1 RO RT = 100Ω 1:(9 - 2) PLL RO RT = 100Ω PLL 7 TxIN 7 (7 + 2):1 7 PWRDWN TxCLK IN TxCLK OUT 7 RxOUT 7 PWRDWN RxCLK OUT RxCLK IN 21:3 SERIALIZER 3:21 DESERIALIZER Figure 15.
PAGE 15
Programmable DC-Balanced 21-Bit Serializers C = -(2 x tB x DSV) / (ln (1 - D) x (RT + RO)) C = -(2 x 13.9ns x 10) / (ln (1 - .02) x (100Ω + 78Ω)) C = 0.0773µF Jitter due to droop is proportional to the droop and transition time: tJ = tT x D (Eq 2) where: tJ = jitter (s) tT = transition time (s) (0% to 100%) D = droop (% of signal amplitude) Jitter due to 2% droop and assumed 1ns transition time is: tJ = 1ns x 0.
PAGE 16
MAX9209/MAX9213 Programmable DC-Balanced 21-Bit Serializers ESD Protection The MAX9209/MAX9213 ESD tolerance is rated for IEC 61000-4-2, Human Body Model and ISO 10605 standards. IEC 61000-4-2 and ISO 10605 specify ESD tolerance for electronic systems. The IEC 61000-4-2 discharge components are CS = 150pF and RD = 330Ω (Figure 16).
PAGE 17
Programmable DC-Balanced 21-Bit Serializers TOP VIEW 36 LVDS GND VCC 14 35 TxOUT2- TxIN13 15 34 TxOUT2+ TxIN14 16 33 TxCLK OUT- GND 17 32 TxCLK OUT+ 31 LVDS GND TxIN16 19 30 PLL GND TxIN17 20 29 PLL VCC 21 28 PLL GND TxIN18 22 VCC 27 PWRDWN TxIN19 23 26 TxCLK IN GND 24 25 TxIN20 TxIN1 TxIN0 DCB/NC 37 38 39 40 32 TxIN12 VCC TxIN13 TxIN14 GND 7 TxIN15 TxIN15 18 41 33 5 6 31 MAX9209 MAX9213 30 8 29 9 28 10 27 11 26 EXPOSED PAD 25 12 LVDS GND TxOU
PAGE 18
MAX9209/MAX9213 Programmable DC-Balanced 21-Bit Serializers Revision History REVISION NUMBER REVISION DATE 3 6/07 — 4 10/07 Removed all references to MAX9211 and MAX9215. 5 3/12 Updated Ordering Information DESCRIPTION PAGES CHANGED 1–5, 9, 14, 15, 18, 19, 20 1–20 1 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.