Datasheet

MAX5884
3.3V, 14-Bit, 200Msps High Dynamic
Performance DAC with CMOS Inputs
4 _______________________________________________________________________________________
Note 1: Nominal full-scale current I
OUT
= 32 ✕ I
REF
.
Note 2: This parameter does not include update-rate depending effects of sin(x)/x filtering inherent in the MAX5884.
Note 3: Parameter measured single ended into a 50Ω termination resistor.
Note 4: Parameter guaranteed by design.
Note 5: Parameter defined as the change in midscale output caused by a ±5% variation in the nominal supply voltage.
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD
= DV
DD
= VCLK = 3.3V, AGND = DGND = CLKGND = 0V, external reference, V
REFIO
= 1.25V, R
L
= 50Ω, I
OUT
= 20mA,
f
CLK
= 200Msps, T
A
= T
MIN
to T
MAX
, unless otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design
and characterization. Typical values are at T
A
= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Data Latency 3.5
Clock
cycles
Minimum Clock Pulse Width High
t
CH
CLKP, CLKN 1.5 ns
Minimum Clock Pulse Width Low
t
CL
CLKP, CLKN 1.5 ns
CMOS LOGIC INPUTS (B0–B13, PD, SEL0, XOR)
Input Logic High V
IH
0.7 x
DV
DD
V
Input Logic Low V
IL
0.3 x
DV
DD
V
Input Leakage Current I
IN
-15 +15 µA
Input Capacitance C
IN
5pF
CLOCK INPUTS (CLKP, CLKN)
Sine wave
≥1.5
Differential Input Voltage Swing V
CLK
Square wave
≥0.5
V
P-P
Differential Input Slew Rate SR
CLK
>100
V/µs
Common-Mode Voltage Range V
COM
1.5
±20%
V
Input Resistance R
CLK
5kΩ
Input Capacitance C
CLK
5pF
POWER SUPPLIES
Analog Supply Voltage Range AV
DD
3.135
3.3
3.465
V
Digital Supply Voltage Range DV
DD
3.135
3.3
3.465
V
Clock Supply Voltage Range V
CLK
3.135
3.3
3.465
V
f
CLK
= 100Msps, f
OUT
= 1MHz 27
Analog Supply Current I
AVDD
Power-down 0.3
mA
f
CLK
= 100Msps, f
OUT
= 1MHz 8 mA
Digital Supply Current I
DVDD
Power-down 10 µA
f
CLK
= 100Msps, f
OUT
= 1MHz 5.5 mA
Clock Supply Current I
VCLK
Power-down 10 µA
f
CLK
= 100Msps, f
OUT
= 1MHz
134
Power Dissipation P
DISS
Power-down 1
mW
Power-Supply Rejection Ratio PSRR
AV
DD
= VCLK = DV
DD
= 3.3V ±5% (Note 5) -0.1 +0.1 %FS/V