Datasheet

MAX5884
3.3V, 14-Bit, 200Msps High Dynamic
Performance DAC with CMOS Inputs
10 ______________________________________________________________________________________
Although not recommended because of additional
noise pickup from the ground plane, for single-ended
operation IOUTP should be selected as the output, with
IOUTN connected to AGND. Note that a single-ended
output configuration has a higher 2nd-order harmonic
distortion at high output frequencies than a differential
output configuration.
Figure 3 displays a simplified diagram of the
MAX5884’s internal output structure.
Clock Inputs (CLKP, CLKN)
The MAX5884 features a flexible differential clock input
(CLKP, CLKN) operating from separate supplies
(VCLK, CLKGND) to achieve the best possible jitter
performance. The two clock inputs can be driven from
a single-ended or a differential clock source. For sin-
gle-ended operation, CLKP should be driven by a logic
source, while CLKN should be bypassed to AGND with
a 0.1µF capacitor.
The CLKP and CLKN pins are internally biased to
VCLK/2. This allows the user to AC-couple clock sources
directly to the device without external resistors to define
the DC level. The input resistance of CLKP and CLKN is
>5kΩ.
See Figure 4 for a convenient and quick way to apply a
differential signal created from a single-ended source
(e.g., HP 8662A signal generator) and a wideband
transformer. These inputs can also be driven from a
CMOS-compatible clock source; however, it is recom-
mended to use sinewave or AC-coupled ECL drive for
best performance.
Data Timing Relationship
Figure 5 shows the timing relationship between differ-
ential, digital CMOS data, clock, and output signals.
The MAX5884 features a 1.25ns hold, a 0.4ns setup,
and a 1.8ns propagation delay time. There is a 3.5
clock-cycle latency between CLKP/CLKN transitioning
high/low and IOUTP/IOUTN.
CMOS-Compatible Digital Inputs (B0–B13)
The MAX5884 features single-ended, CMOS-compatible
receivers on the bus input interface. These CMOS inputs
(B0–B13) allow for a voltage swing of 3.3V.
Segment Shuffling (SEL0)
Segment shuffling can improve the SFDR of the
MAX5884 at higher output frequencies and amplitudes.
Note that an improvement in SFDR can only be
achieved at the cost of a slight increase in the DAC’s
noise floor.
Pin SEL0 controls the segment-shuffling function. If
SEL0 is pulled low, the segment-shuffling function of
the DAC is disabled. SEL0 can also be left open,
because an internal pulldown resistor helps to deacti-
vate the segment-shuffling feature. To activate the
MAX5884 segment-shuffling function, SEL0 must be
pulled high.
XOR Function (XOR)
The MAX5884 is equipped with a single-ended, CMOS-
compatible XOR input, which may be left open (XOR
provides an internal pulldown resistor) or pulled down to
DGND, if not used. Input data is XORed with the bit
applied to the XOR pin. Pulling XOR high inverts the
input data. Pulling XOR low leaves the input data nonin-
verted. By applying a pseudorandom bit stream to XOR
and applying inverted data when XOR is high, the bit
transitions of the digital input data can be decorrelated
from the DAC output. This allows the user to trou-
bleshoot possible spurious or harmonic distortion
degradation due to digital feedthrough on the PC board.
SINGLE-ENDED
CLOCK SOURCE
(e.g., HP 8662A)
1:1
WIDEBAND RF TRANSFORMER
PERFORMS SINGLE-ENDED TO
DIFFERENTIAL CONVERSION.
TO
DAC
CLKP
0.1µF
0.1µF
CLKN
CLKGND
25Ω
25Ω
Figure 4. Differential Clock Signal Generation
I
OUT
I
OUT
IOUTN IOUTP
CURRENT
SOURCES
CURRENT
SWITCHES
AV
DD
Figure 3. Simplified Analog Output Structure