Datasheet

MAX17030/MAX17036
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
______________________________________________________________________________________ 21
When the main and other phase current-sense signals
(V
CM
= V
CMP
- V
CMN
and V
CS
= V
CSP
- V
CSM
) become
unbalanced, the transconductance amplifiers adjust the
other phase’s on-time, which increases or decreases
the phase inductor current until the current-sense sig-
nals are properly balanced:
where V
CCI
is the internal integrator node for each
slave’s current-balance integrator, and Z
CCI
is the
effective impedance at that node.
During phase overlap, t
ON
is calculated based on
phase 1’s on-time requirements, but reduced by 33%
when operating with three phases.
For a 3-phase regulator, each phase cannot be
enabled until the other 2 phases have completed their
on-time and the minimum off-times have expired. As
such, the minimum period is limited by 3 x (t
ON
+
t
OFF(MIN)
). Maximum t
ON
is dependent on minimum V
IN
and maximum output voltage:
T
SW(MIN)
= N
PH
x (t
ON(MAX)
+ t
OFF(MIN)
)
where:
t
ON(MAX)
= V
FB(MAX)
/V
IN(MIN
x T
SW(MIN)
so:
T
SW(MIN)
= t
OFF(MIN)
/[1/N
PH
– V
IN(MAX)
/V
IN(MIN)
]
Hence, for a 7V input and 1.1V output, 500kHz is the
maximum switching frequency. Running at this limit is
not desirable as there is no room to allow the regulator
to make adjustments without triggering phase overlap.
For a 3-phase, high-current application with minimum
8V input, the practical switching frequency is 300kHz.
On-times translate only roughly to switching frequen-
cies. The on-times guaranteed in the Electrical
Characteristics are influenced by parasitics in the con-
duction paths and propagation delays. For loads above
the critical conduction point, where the dead-time effect
(LX flying high and conducting through the high-side
FET body diode) is no longer a factor, the actual
switching frequency (per phase) is:
where V
DIS
and V
CHG
are the sum of the parasitic volt-
age drops in the inductor discharge and charge paths,
including MOSFET, inductor, and PCB resistances;
V
CHG
is the sum of the parasitic voltage drops in the
inductor charge path, including high-side switch,
inductor, and PCB resistances; and t
ON
is the on-time
as determined above.
Current Sense
The MAX17030/MAX17036 sense the output current of
each phase allowing the use of current-sense resistors
on inductor DCR as the current-sense element. Low-
offset amplifiers are used for current balance, voltage-
positioning gain, and current limit.
Using the DC resistance (R
DCR
) of the output inductor
allows higher efficiency. The initial tolerance and tem-
perature coefficient of the inductor’s DCR must be
accounted for in the output-voltage droop-error budget
and current monitor. This current-sense method uses
an RC filtering network to extract the current information
from the output inductor (see Figure 4). The RC network
should match the inductor’s time constant (L/R
DCR
):
and:
where R
CS
is the required current-sense resistance,
and R
DCR
is the inductor’s series DC resistance. Use
the typical inductance and R
DCR
values provided by
the inductor manufacturer. To minimize the current-
sense error due to the current-sense inputs’ bias current
(I
CSP_
and I
CSN_
), choose R1//R2 to be less than 2kΩ
and use the above equation to determine the sense
capacitance (C
EQ
). Choose capacitors with 5% toler-
ance and resistors with 1% tolerance specifications.
Temperature compensation is recommended for this
current-sense method. See the Voltage Positioning and
Loop Compensation section for detailed information.
When using a current-sense resistor for accurate out-
put-voltage positioning, the circuit requires a differential
RC filter to eliminate the AC voltage step caused by the
equivalent series inductance (L
ESL
) of the current-
sense resistor (see Figure 4). The ESL induced voltage
step might affect the average current-sense voltage.
The RC filter’s time constant should match the L
ESL
/
R
SENSE
time constant formed by the current-sense
resistor’s parasitic inductance:
L
R
CR
ESL
SENSE
EQ EQ
=
R
L
CRR
CS
EQ
=+
⎡
⎣
⎢
⎤
⎦
⎥
1
1
1
2
R
R
RR
R
CS DCR
=
+
⎛
⎝
⎜
⎞
⎠
⎟
2
12
f
VV
tVV V
SW
OUT DIS
ON IN DIS CHG
=
+
()
+−
()
tT
VV
V
T
V
ON SEC SW
CCI
IN
SW
FB
()
.
.
=
+
⎛
⎝
⎜
⎞
⎠
⎟
=
+
0 075
00
775V
V
T
IZ
V
IN
SW
CCI CCI
IN
⎛
⎝
⎜
⎞
⎠
⎟
+
⎛
⎝
⎜
⎞
⎠
⎟
= Main On-ttime Secondary Current Balance Correctio
()
+ nn
()