Datasheet

MAX17030/MAX17036
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
14 ______________________________________________________________________________________
Pin Description (continued)
PIN NAME FUNCTION
This low-voltage logic input indicates power usage and sets the operating mode together
with DPRSLPVR as shown in the truth table below. While DPRSLPVR is low, if P SI is forced low, the
controller is immediately set to (N-1)-phase forced-PWM mode. The controller returns to N-phase
forced-PWM mode when P SI is forced high.
The controller is in N-phase skip mode during startup including boot mode, but is in N-phase forced-
PWM mode during the transition from boot mode to VID mode, during soft-shutdown, irrespective of
the DPRSLPVR and P SI logic levels. However, if phases 2 and 3 are disabled by connecting CSP2,
CSP3 to VCC, then only phase 1 is active in the above modes.
DPRSLPVR PSI MODE
15 PSI
1
0
0
X
0
1
Very low current (1-phase skip)
Intermediate power potential (N-1-phase PWM)
Max power potential (full-phase PWM: N-phase or 1 phase as set by user
at CSP2, CSP3)
16 TON
Switching Frequency Setting Input. An external resistor between the input power source and this pin
sets the switching frequency according to the following equation:
f
SW
= 1/(C
TON
x (R
TON
+ 6.5kΩ))
where C
TON
= 16.26pF.
The external resistor must also satisfy the requirement [V
IN(MIN)
/R
TON
] ≥ 10μA where V
IN(MIN)
is the
minimum V
IN
value expected in the application.
TON is high impedance in shutdown.
17 CLKEN
C l ock E nab l e Op en- D r ai n Log i c O utp ut P ow er ed b y V
3 P 3
. Thi s i nver ted l og i c outp ut i nd i cates w hen the
outp ut vol tag e sensed at FB i s i n r eg ul ati on. C LKEN i s for ced hi g h i n shutd ow n and d ur i ng soft- star t and
soft- stop tr ansi ti ons. C LKEN i s for ced l ow d ur i ng d ynam i c V ID tr ansi ti ons and for an ad d i ti onal 20μs after
the tr ansi ti on i s com p l eted . C LKEN i s the i nver se of P WRGD , excep t for the 5m s P WRG D star tup d el ay
p er i od after C LKEN i s p ul l ed l ow . S ee the star tup ti m i ng d i ag r am ( Fi g ur e 9) . The C LKEN up p er thr eshol d
i s b l anked d ur i ng any d ow nw ar d outp ut- vol tag e tr ansi ti on that hap p ens w hen the contr ol l er i s i n ski p
m od e, and stays b l anked unti l the sl ew - r ate- contr ol l ed i nter nal - tr ansi ti on- r el ated P W RG D b l anki ng p er i od
i s com p l ete and the outp ut r eaches r eg ul ati on.
18 PWRGD
Open-Drain Power-Good Output. After output-voltage transitions, except during power-up and power-
down, if FB is in regulation, then PWRGD is high impedance.
PWRGD is low during startup, continues to be low while the output is at the boot voltage, and stays
low until 5ms (typ) after CLKEN goes low, after which it starts monitoring the FB voltage and goes
high if FB is within the PWRGD threshold window.
PWRGD is forced low during soft-shutdown and while in shutdown. PWRGD is forced high impedance
whenever the slew-rate controller is active (output-voltage transitions), and continues to be forced
high impedance for an additional 20μs after the transition is completed.
The PWRGD upper threshold is blanked during any downward output-voltage transition that happens
when the controller is in skip mode, and stays blanked until the slew-rate-controlled internal-transition-
related PWRGD blanking period is complete and the output reaches regulation.
A pullup resistor on PWRGD causes additional finite shutdown current.
19 DRSKP
Driver Skip Control Output. Push/pull logic output that controls the operating mode of the skip-mode
driver IC. DRSKP swings from V
DD
to GND. When DRSKP is high, the driver ICs operate in forced-
PWM mode. When DRSKP is low, the driver ICs enable their zero-crossing comparators and operate
in pulse-skipping mode. DRSKP goes low at the end of the soft-shutdown sequence, instructing the
external drivers to shut down.