Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal LQFP 48

General Description

The MAX1316–MAX1318/MAX1320–MAX1322/MAX1324–

MAX1326 14-bit, analog-to-digital converters (ADCs) offer

two, four, or eight independent input channels.

Independent track/hold (T/H) circuitry provides simultane-

ous sampling for each channel. The MAX1316/

MAX1317/MAX1318 have a 0 to +5V input range with

±6.0V fault-tolerant inputs. The MAX1320/MAX1321/

MAX1322 have a ±5V input range with ±16.5V fault-toler-

ant inputs. The MAX1324/MAX1325/MAX1326 have a

±10V input range with ±16.5V fault-tolerant inputs. These

ADCs convert two channels in 2µs, and up to eight chan-

nels in 3.8µs, and have an 8-channel throughput of

250ksps per channel. Other features include a 10MHz

T/H input bandwidth, internal clock, internal (+2.5V) or

external (+2.0V to +3.0V) reference, and power-

saving modes.

A 16.6MHz, 14-bit, bidirectional, parallel interface pro-

vides the conversion results and accepts digital config-

uration inputs.

These devices operate from a +4.75V to +5.25V analog

supply and a separate +2.7V to +5.25V digital supply,

and consume less than 50mA total supply current.

These devices come in a 48-pin LQFP package and oper-

ate over the extended -40°C to +85°C temperature range.

Applications

Multiphase Motor Control

Power-Grid Synchronization

Power-Factor Monitoring and Correction

Vibration and Waveform Analysis

Features

♦ 8-/4-/2-Channel, 14-Bit ADCs

±1.5 LSB INL, ±1 LSB DNL, No Missing Codes

90dBc SFDR, -86dBc THD, 76.5dB SINAD, 77dB

SNR at 100kHz Input

♦ On-Chip T/H Circuit for Each Channel

10ns Aperture Delay

50ps Channel-to-Channel T/H Matching

♦ Fast Conversion Time

One Channel in 1.6µs

Two Channels in 1.9µs

Four Channels in 2.5µs

Eight Channels in 3.7µs

♦ High Throughput

526ksps/ch for One Channel

455ksps/ch for Two Channels

357ksps/ch for Four Channels

250ksps/ch for Eight Channels

♦ Flexible Input Ranges

0 to +5V (MAX1316/MAX1317/MAX1318)

±5V (MAX1320/MAX1321/MAX1322)

±10V (MAX1324/MAX1325/MAX1326)

♦ No Calibration Needed

♦ 14-Bit, High-Speed, Parallel Interface

♦ Internal or External Clock

♦ +2.5V Internal Reference or +2.0V to +3.0V

External Reference

♦ +5V Analog Supply, +3V to +5V Digital Supply

46mA Analog Supply Current (typ)

1.6mA Digital Supply Current (max)

Shutdown and Power-Saving Modes

♦ 48-Pin LQFP Package (7mm x 7mm Footprint)

MAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326

8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs

with ±10V, ±5V, and 0 to +5V Analog Input Ranges

________________________________________________________________

Maxim Integrated Products

Ordering Information

Selector Guide

19-3157; Rev 4; 10/08

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,

or visit Maxim’s website at www.maxim-ic.com.

Pin Configurations and Typical Operating Circuits appear at

end of data sheet.

PART TEMP RANGE PIN-PACKAGE

MAX1316ECM -40°C to +85°C 48 LQFP

MAX1317ECM -40°C to +85°C 48 LQFP

MAX1318ECM -40°C to +85°C 48 LQFP

MAX1320ECM -40°C to +85°C 48 LQFP

MAX1321ECM -40°C to +85°C 48 LQFP

MAX1322ECM -40°C to +85°C 48 LQFP

MAX1324ECM -40°C to +85°C 48 LQFP

MAX1325ECM -40°C to +85°C 48 LQFP

MAX1326ECM -40°C to +85°C 48 LQFP

PART INPUT RANGE (V) CHANNEL COUNT

MAX1316ECM 0 to +5 8

MAX1317ECM 0 to +5 4

MAX1318ECM 0 to +5 2

MAX1320ECM ±5 8

MAX1321ECM ±5 4

MAX1322ECM ±5 2

MAX1324ECM ±10 8

MAX1325ECM ±10 4

MAX1326ECM ±10 2

Summary of content (27 pages)

PAGE 1
9-3157; Rev 4; 10/08 8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges Features The MAX1316–MAX1318/MAX1320–MAX1322/MAX1324– MAX1326 14-bit, analog-to-digital converters (ADCs) offer two, four, or eight independent input channels. Independent track/hold (T/H) circuitry provides simultaneous sampling for each channel. The MAX1316/ MAX1317/MAX1318 have a 0 to +5V input range with ±6.0V fault-tolerant inputs.
PAGE 2
MAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326 8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges ABSOLUTE MAXIMUM RATINGS REF+, COM, REF- to AGND.....................-0.3V to (AVDD + 0.3V) D0–D13 to DGND ....................................-0.3V to (DVDD + 0.3V) Maximum Current into Any Pin Except AVDD, DVDD, AGND, DGND...............................................................±50mA Continuous Power Dissipation LQFP (derate 22.7mW/°C above +70°C) ....
PAGE 3
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges (VAVDD = +5V, VDVDD = +3V, VAGND = VDGND = 0, VREF = VREFMS = +2.5V (external reference), CREF = CREFMS = 0.1µF, CREF+ = CREF- = 0.1µF, CREF+-to-REF- = 2.2µF || 0.1µF, C COM = 2.2µF || 0.1µF, C MSV = 2.2µF || 0.
PAGE 4
MAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326 8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges ELECTRICAL CHARACTERISTICS (continued) (VAVDD = +5V, VDVDD = +3V, VAGND = VDGND = 0, VREF = VREFMS = +2.5V (external reference), CREF = CREFMS = 0.1µF, CREF+ = CREF- = 0.1µF, CREF+-to-REF- = 2.2µF || 0.1µF, C COM = 2.2µF || 0.1µF, C MSV = 2.2µF || 0.
PAGE 5
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges PARAMETER SYMBOL CONDITIONS MIN Internal clock Time-to-First-Conversion Result tCONV Time-to-Next-Conversion Result tNEXT CONVST Pulse-Width Low (Acquisition Time) tACQ TYP MAX 1.6 1.8 External clock, Figure 6 16 Internal clock 0.3 External clock, Figure 6 (Note 9) µs Clock cycles 0.36 µs Clock cycles 3 0.
PAGE 6
TIMING CHARACTERISTICS (Figures 3, 4, 5, 6 and 7) (Tables 1, 3) (continued) Shutdown current is measured with analog input floating. The large amplitude of the maximum shutdown current specification is due to automatic test equipment limitations. Note 8: Defined as the change in positive full scale caused by ±5% variation in the nominal supply voltage. Note 9: CONVST must remain low for at least the acquisition period. The maximum acquisition time is limited by internal capacitor droop.
PAGE 7
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE 2.5001 2.501 VREF (V) 2.502 2.5000 2.500 0.5 0 -0.5 2.4999 2.499 2.4998 2.498 2.4997 2.497 -1.5 2.4996 2.496 -2.0 4.8 4.9 5.0 5.1 5.2 5.3 -40 -15 AVDD (V) 35 60 85 OFFSET ERROR vs. TEMPERATURE -0.01 14 13 12 11 -0.02 NORMALIZED AT TA = +25°C 35 TEMPERATURE (°C) 85 5.25 0.07 0.06 0.05 0.04 0.02 0.01 9 60 5.15 0.03 10 -0.
PAGE 8
Typical Operating Characteristics (continued) (AVDD = +5V, DVDD = +3V, AGND = DGND = 0V, VREF = VREFMS = +2.5V (external reference), see the Typical Operating Circuits section, fCLK = 10MHz, 50% duty cycle, INTCLK/EXTCLK = AGND (external clock), SHDN = DGND, TA = +25°C, unless otherwise noted.) 77 76 75 74 -100 -120 0.05 0.10 0.15 0.20 75 74 73 72 72 71 71 70 8 0.25 10 12 14 16 18 8 20 10 12 14 16 18 FREQUENCY (MHz) fCLK (MHz) fCLK (MHz) EFFECTIVE NUMBER OF BITS vs.
PAGE 9
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges CONVERSION TIME vs. TEMPERATURE 1.4 1.2 1.0 0.8 0.6 tNEXT INTERNAL CLOCK 1.6 4500 4000 3000 1.2 1.0 0.8 0.4 1000 0.2 500 0 5.000 5.125 5.250 0 -40 -15 2306 2000 1562 1500 tNEXT 0.6 2500 0.2 4.875 3815 3500 1.4 0.4 0 4.750 MAX1316 toc20 tCONV 1.8 CONVERSION TIME (µs) CONVERSION TIME (µs) 1.6 2.0 COUNTS INTERNAL CLOCK tCONV 1.8 MAX1316 toc18 2.
PAGE 10
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges MAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326 Pin Description (continued) PIN MAX1316 MAX1320 MAX1324 MAX1317 MAX1321 MAX1325 MAX1318 MAX1322 MAX1326 NAME 10 — — CH5 Channel 5 Analog Input 11 — — CH6 Channel 6 Analog Input 12 — — CH7 Channel 7 Analog Input 13 INTCLK/ EXTCLK Clock-Mode Select Input. Use INTCLK/EXTCLK to select the internal or external conversion clock.
PAGE 11
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges PIN MAX1316 MAX1320 MAX1324 MAX1317 MAX1321 MAX1325 MAX1318 MAX1322 MAX1326 NAME 27 27 27 D3 Digital I/O Bit 3 of 14-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1. 28 28 28 D4 Digital I/O Bit 4 of 14-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1. 29 29 29 D5 Digital I/O Bit 5 of 14-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.
PAGE 12
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges MAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326 Pin Description (continued) PIN 12 MAX1316 MAX1320 MAX1324 MAX1317 MAX1321 MAX1325 MAX1318 MAX1322 MAX1326 NAME 41 41 41 EOLC 42 42 42 RD Read Input. When RD and CS go low, the device initiates a read command of the parallel data buses, D0–D13. D0–D13 are high impedance while either RD or CS is high. 43 43 43 WR Write Input.
PAGE 13
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges CH0 S/H 8 x 14 SRAM 14-BIT ADC 8x1 MUX CH7 DVDD D13 OUTPUT DRIVERS S/H D8 D7 D0 MSV CONFIGURATION REGISTER REF+ COM REF- * WR CS INTERFACE AND CONTROL RD CONVST SHDN 5kΩ CLK REF ALLON 5kΩ EOC REFMS 2.500V EOLC DGND INTCLK/EXTCLK AGND *SWITCH CLOSED ON UNIPOLAR DEVICES, OPEN ON BIPOLAR DEVICES Figure 1.
PAGE 14
MAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326 8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges To improve the input-signal bandwidth under AC conditions, drive the input with a wideband buffer (>50MHz) that can drive the ADC’s input capacitance and settle quickly. For example, the MAX4265 can be used for +5V unipolar devices, or the MAX4350 can be used for ±5V bipolar inputs. The T/H aperture delay is typically 13ns.
PAGE 15
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges SAMPLE CONVST WR DUMMY CONVERSION START LATCH ACTUAL CONVERSION START DATA-IN CHANGES ONE OR MORE CHANNELS FROM POWER-DOWN TO ACTIVE MODE D0–D7 DATA-IN 1 2 3 4 5 14 15 1 CLK >14 CYCLES EOC EOLC Figure 3. Software Channel Wake-Up Timing (ALLON = 0) Clock Modes These devices provide an internal clock of 10MHz (typ). Alternatively, an external clock can be used.
PAGE 16
MAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326 8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges Table 2. Configuration Register PART NO.
PAGE 17
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges Reading a Conversion Result Reading During a Conversion Figures 5 and 6 show the interface signals for initiating a read operation during a conversion cycle. These figures show two channels selected for conversion. If more channels are selected, the results are available successively every third clock cycle. CS can be low at all times; it can be low during the RD cycles, or it can be the same as RD.
PAGE 18
MAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326 8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges SAMPLE t13 tACQ CONVST HOLD TRACK t19 TRACK t16 1 CLK 2 3 t17 16 17 18 t18 19 20 21 22 23 EOC t12 tQUIET RD t10 t3 D0–D13 CH0 CH1 t11 Figure 6.
PAGE 19
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges Power-Up Reset At power-up, all channels are selected for conversion (see the Configuration Register section). After applying power, allow a 1.0ms wake-up time to elapse before initiating the first conversion. Then, hold CONVST high for at least 2.0µs after the wake-up time is complete. If using an external clock, apply 20 clock pulses to CLK with CONVST high before initiating the first conversion.
PAGE 20
No other digital system ground should be connected to this single-point analog ground. The ground return to the power supply for this ground should be low impedance and as short as possible for noise-free operation. High-frequency noise in the VDD power supply may affect the high-speed comparator in the ADC. Bypass these supplies to the single-point analog ground with 0.1µF and 2.2µF bypass capacitors close to the device.
PAGE 21
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges TWO'S COMPLEMENT BINARY OUTPUT CODE 4 x VREF 0x1FFF 0x1FFE 0x1FFD 0x1FFC 0x0001 0x0000 0x3FFF 4 x VREF 0x2003 0x2002 0x2001 0x2000 1 LSB = 4 x VREF 2 -8192 -8190 -1 0 +1 (MSV) 14 +8189 +8191 INPUT VOLTAGE (VCH_ - VMSV IN LSBs) Figure 10. ±5V Bipolar Transfer Function The input range is centered about V MSV. Normally, MSV = AGND, and the input is symmetrical about zero.
PAGE 22
Differential Nonlinearity Differential nonlinearity (DNL) is the difference between an actual step width and the ideal value of 1 LSB. For these devices, the DNL of each digital output code is measured and the worst-case value is reported in the Electrical Characteristics table. A DNL error specification of less than ±1 LSB guarantees no missing codes and a monotonic transfer function.
PAGE 23
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges Aperture Delay Aperture delay (tAD) is the time delay from the sampling clock edge to the instant when an actual sample is taken. ⎡ ⎤ SignalRMS SINAD(dB) = 20 × log ⎢ ⎥ ⎣ (Noise + Distortion)RMS ⎦ Aperture Jitter (tAJ) is the sample-to-sample variation in aperture delay.
PAGE 24
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges MAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326 Typical Operating Circuits 13 DVDD INTCLK/EXTCLK 38 +5V 0.1µF 0.1µF 1 AVDD 0.1µF 15 0.1µF 17 AVDD MSV 18 REFMS 19 REF 20 REF+ 22 REF0.1µF CLK EOLC D13 D12 2.
PAGE 25
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges 13 DVDD INTCLK/EXTCLK 38 +5V 0.1µF 0.1µF 1 AVDD 0.1µF 15 0.1µF 17 AVDD AVDD MAX1320 MAX1321 MAX1322 MAX1324 MAX1325 MAX1326 DGND CS RD WR 6 BIPOLAR CONFIGURATION 0.01µF 18 19 MSV REFMS REF CONVST SHDN ALLON CLK 0.1µF 20 EOC REF+ EOLC 22 REF0.
PAGE 26
CH4 CH5 CH6 9 28 10 27 D5 D4 D3 11 26 CH7 12 25 DVDD D13 10 27 D5 D4 D3 11 26 I.C. 12 25 13 DVDD D13 3 34 CH0 CH1 MSV 4 33 5 32 I.C. I.C. I.C. I.C. I.C. I.C. 7 31 MAX1318 MAX1322 MAX1326 30 29 24 D0 22 23 REFMS REF REF+ 21 25 COM REFAGND 26 12 20 27 11 19 28 10 18 9 17 4-CHANNEL LQFP 37 38 39 EOLC EOC DGND 40 41 42 CS WR RD 43 44 45 46 ALLON SHDN CLK CONVST 48 35 16 37 38 28 36 15 39 EOLC EOC DGND 41 9 2 14 40 WR RD I.C. I.C. I.C.
PAGE 27
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges REVISION NUMBER REVISION DATE DESCRIPTION PAGES CHANGED 3 2/07 Corrected units for input resistance in EC table 3 4 10/08 Changed specs for analog and digital supply current in EC table 4 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.