User guide

Double-width mode: 40:40, 64:64, or 66:64
3. Select Phase_compensation in the TX and RX FIFO mode list.
4. If you need the Scrambler and Descrambler features, enable Block Synchronize and use the 66:32,
66:40, or 66:64 gear ratio.
TX Bit Slip
The bit slip feature in the TX gearbox allows you to slip the transmitter bits before they are sent to the
serializer.
The value specified on the TX bit slip bus indicates the number of bit slips. The minimum slip is one UI.
The maximum number of bits slipped is equal to the FPGA fabric-to-transceiver interface width minus 1.
For example, if the FPGA fabric-to-transceiver interface width is 64 bits, the bit slip logic can slip a
maximum of 63 bits. Each channel has 6 bits to determine the number of bits to slip. The TX bit slip bus is
a level-sensitive port, so the TX serial data is bit slipped statically by TX bit slip port assignments. Each TX
channel has its own TX bit slip assignment and the bit slip amount is relative to the other TX channels.
You can improve lane-to-lane skew by assigning TX bit slip ports with proper values.
The following figure shows the effect of slipping tx_serial_data[0] by one UI to reduce the skew with
tx_serial_data[1]. After the bit slip, tx_serial_data[0] and tx_serial_data[1] are aligned.
Figure 2-106: TX Bit Slip
tx_serial_data[0] (Clock Pattern)
tx_enh_bitslip[0]
tx_serial_data[0] (Before)
tx_enh_bitslip[0]
tx_serial_data[0] (After)
tx_serial_data[1]
0000000
0000001
1 UI
TX Polarity Inversion
Use the TX polarity inversion feature to swap the positive and negative signals of a serial differential link if
they were erroneously swapped during board layout. To enable TX polarity inversion, select the Enable
TX data polarity inversion option in the Gearbox section of Qsys. It can also be dynamically controlled
with dynamic reconfiguration.
RX Bit Slip
The RX bit slip in the RX gearbox allows you to slip the recovered data.
An active high edge on the rx_bitslip port (synchronous to rx_clkout) changes the word boundary,
shifting rx_parallel_data one bit at a time. Use the rx_bitslip port with its own word aligning logic.
You can verify the word alignment by monitoring rx_parallel_data. Using the RX bit slip feature is
optional.
UG-01143
2015.05.11
TX Bit Slip
2-289
Implementing Protocols in Arria 10 Transceivers
Altera Corporation
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