User guide

Figure 2-101: Transceiver Channel Datapath and Clocking for Basic (Enhanced PCS) Configuration
Transmitter Enhanced PCSTransmitter PMA
Receiver PMA
Receiver Enhanced PCS
TX
Gearbox
tx_serial_data
(10.3125 Gbps)
Serializer
Interlaken
Disparity Generator
Scrambler (3)
Descrambler (3)
PRBS
Generator
PRP
Generator
rx_serial_data
Deserializer
CDR
Interlaken
Disparity Checker
Block
Synchronizer (1)
Interlaken
Frame Sync
RX
Gearbox
PRBS
Verifier
Transcode
Decoder
KR FEC RX
Gearbox
KR FEC
Decoder
KR FEC
Block Sync
KR FEC
Descrambler
Parallel Clock
Serial Clock
Parallel and Serial Clocks
Clock Divider
Parallel and Serial Clocks
Clock Generation Block (CGB)
Serial Clock
ATX PLL
fPLL
CMU PLL
64B/66B Decoder
and RX SM
10GBASE-R
BER Checker
PRP
rx_pma_div_clkout
tx_pma_div_clkout
Verifier
rx_clkout
Enhanced PCS
TX FIFO
Enhanced PCS
RX FIFO
Interlaken
Frame Generator
Interlaken
CRC32 Generator
Interlaken
CRC32 Checker
64B/66B Encoder
and TX SM
FPGA
Fabric
tx_clkout
KR FEC
TX Gearbox
KR FEC
Scrambler
KR FEC
Encoder
Transcode
Encoder
Parallel Clock (322.265625 MHz)
Parallel Clock (322.265625 MHz)
(5156.25 MHz) =
Data rate/2 (2)
Input Reference Clock
32-bit
data
32-bit
data
tx_coreclkin
322.265625 MHz
rx_coreclkin
322.265625 MHz
32
32
32
32
Notes:
1. Can be enabled or disabled based on the gearbox ratio selected
2. Depends on the value of the clock division factor chosen
3. To use the Scrambler and Descrambler, you must use a 66:32, 66:40, or 66:64 gear ratio and the Block Synchronizer must be enabled
2-280
Using the "Basic (Enhanced PCS)" and "Basic with KR FEC" Configurations...
UG-01143
2015.05.11
Altera Corporation
Implementing Protocols in Arria 10 Transceivers
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