Specifications

VLSI
Solution
y
VS1053b
VS1053B
8. FUNCTIONAL DESCRIPTION
8.7.4 SCI CLOCKF (RW)
The operation of SCI CLOCKF has changed slightly in VS1053b compared to VS1003 and VS1033.
Multiplier 1.5× and addition 0.5× have been removed to allow higher clocks to be configured.
SCI CLOCKF bits
Name Bits Description
SC MULT 15:13 Clock multiplier
SC ADD 12:11 Allowed multiplier addition
SC FREQ 10: 0 Clock frequency
SC MULT activates the built-in clock multiplier. This will multiply XTALI to create a higher CLKI.
The values are as follows:
SC MULT MASK CLKI
0 0x0000 XTALI
1 0x2000 XTALI×2.0
2 0x4000 XTALI×2.5
3 0x6000 XTALI×3.0
4 0x8000 XTALI×3.5
5 0xa000 XTALI×4.0
6 0xc000 XTALI×4.5
7 0xe000 XTALI×5.0
SC ADD tells, how much the decoder firmware is allowed to add to the multiplier specified by SC MULT
if more cycles are temporarily needed to decode a WMA or AAC stream. The values are:
SC ADD MASK Multiplier addition
0 0x0000 No modification is allowed
1 0x0800 1.0×
2 0x1000 1.5×
3 0x1800 2.0×
SC FREQ is used to tell if the input clock XTALI is running at something else than 12.288 MHz. XTALI
is set in 4 kHz steps. The formula for calculating the correct value for this register is
XT ALI−8000000
4000
(XTALI is in Hz).
Note: The default value 0 is assumed to mean XTALI=12.288 MHz.
Note: because maximum samplerate is
XT ALI
256
, all samplerates are not available if XTALI < 12.288
MHz.
Note: Automatic clock change can only happen when decoding WMA and AAC files. Automatic clock
change is done one 0.5× at a time. This does not cause a drop to 1.0× clock and you can use the same
SCI and SDI clock throughout the file.
Example: If SCI CLOCKF is 0x9BE8, SC MULT = 4, SC ADD = 3 and SC FREQ = 0x3E8 = 1000.
This means that XTALI = 1000×4000+8000000 = 12 MHz. The clock multiplier is set to 3.5×XTALI =
42 MHz, and the maximum allowed multiplier that the firmware may automatically choose to use is
(3.5 + 2.0)×XTALI = 66 MHz.
Version 1.01, 2008-05-22 42