Datasheet

TPS75005
SBVS144C –NOVEMBER 2011–REVISED APRIL 2012 www.ti.com
ELECTRICAL CHARACTERISTICS
Over operating temperature range of T
J
= –40 °C to +125 °C, with 4.0 V ≤ V
IN
≤ 6.5 V, V
OUT1_S
= V
OUT1
, V
OUT2_S
= V
OUT2
, V
EN
=
V
IN
, CT1 = OPEN, CT2 = OPEN, SS1 = OPEN, SS2 = OPEN, PG = pulled up to V
OUT2
through 100-kΩ resistor, TEST =
pulled up to V
OUT2
through 100-kΩ resistor, V
DET
= pulled up to V
IN
through 100-kΩ resistor, V
MON
= V
IN
, C
OUT1
= 10 µF, C
OUT2
= 10 µF, R
OUT1
= 1 kΩ to GND
(1)
, R
OUT2
= 1 kΩ to GND
(1)
, and V
SET
= SEQ = GND, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
COMPLETE DEVICE
V
IN
Input voltage range 3.75 6.5 V
I
GND
GND current I
OUT1
= I
OUT2
= 500 mA, V
SET
= V
IN
or GND 500 µA
I
Q
Quiescent GND current I
OUT1
= I
OUT2
= 0 A, V
SET
= V
IN
or GND 175 µA
I
SHDN
Shutdown ground current V
IN
= 6.5 V, no pull-up resistors at PG, VDET, TEST pins 17 40 µA
V
SVS3
VMON supervisor threshold 1.181 1.206 1.230 V
ΔV
SVS3
VMON supervisor hysteresis Relative to V
SVS3
+ 4 mV
V
IH
High-level input voltage For EN, SEQ, and VSET pins 2.0 V
V
IL
Low-level input voltage For EN, SEQ, and VSET pins 0 0.8 V
For SEQ and VSET pins, V
SEQ
= V
SET
= 2.0 V – 0.1 0.1
I
IN
Logic input current µA
For EN pin – 0.2 0.2
Load current 1 mA into PG, TEST, and VDET pins
V
OL
Low-level output voltage 0.3 V
force V
OUT1
< V
SVS1
, V
MON
= 0.5 V
Releasing: V
IN
rising 3.4 3.75 V
UVLO Undervoltage lock out
Locking: hysteresis, V
IN
falling 60 mV
Temperature rising to shutdown +165 °C
T
TSD
Thermal shutdown temperature
Hysteresis, temperature falling to release shutdown +145 °C
t
DVS
VSET transition time
(2)
40 µs
LDO1 (1.8 V or 1.9 V Selectable by VSET Pin)
1.881 1.919 1.957
V
SET
= H, 4.0 V ≤ V
IN
≤ 6.5 V, 1 mA ≤ I
OUT1
≤ 500 mA V
(99%) (101%) (103%)
V
OUT1
LDO1 output voltage accuracy
1.782 1.818 1.854
V
SET
= L, 4.0 V ≤ V
IN
≤ 6.5 V, 1 mA ≤ I
OUT1
≤ 500 mA V
(99%) (101%) (103%)
ΔV
OUT1
/ΔV
IN
LDO1 line regulation 4.0 V ≤ V
IN
≤ 6.5 V, I
OUT1
= 1 mA 122 µV/V
ΔV
OUT1
/ΔI
OUT1
LDO1 load regulation 1 mA ≤ I
OUT1
≤ 500 mA 29 µV/mA
I
CL1
LDO1 current limit V
OUT1
= 0.9 × V
OUT1(NOM)
, 4.5 V < V
IN
< 6.5 V 900 mA
V
SET
= H, 4.0 V ≤ V
IN
≤ 6.5 V 1.805 1.881
V
Force V
OUT1
(decreasing) (95%) (99%)
V
SVS1
LDO1 supervisor threshold
V
SET
= L, 4.0 V ≤ V
IN
≤ 6.5 V 1.710 1.782
V
Force V
OUT1
(decreasing) (95%) (99%)
ΔV
SVS1
LDO1 supervisor hysteresis Relative to V
SVS1
0.3 %
LDO1 supervisor minimum pulse
t
W(SVS1)
V
OUT1
= 100% → 90% → 100% 3.3 µs
width to Sense
From (V
OUT1
> V
SVS1
) event to PG ↑ with SEQ = H,
t
D(SVS1)
LDO1 supervisor delay time 33 µs
C
CT1
= (open)
Any capacitor connected between CT1 and GND,
I
CT1
CT1 charging current 0.3 1 µA
0.2 V ≤ V
CT1
≤ 1.0 V
V
CT1
CT1 timeout threshold Any capacitor connected between CT1 and GND 1.05 1.206 1.35 V
t
SS1
LDO1 soft-start time V
OUT1
waveform from 0% to 95%, C
SS1
= (open) 260 µs
Any capacitor connected between SS1 and GND,
I
SS1
SS1 charging current 0.3 0.8 µA
0.2 V ≤ V
SS1
≤ 1.0 V
LDO1 active pull-down ON
R
PD1
EN = GND, V
OUT1
= 1.8 V 225 360 475 Ω
resistance
LDO1 power-down detector
V
DOWN1
0.3 V
accuracy
(1) These 1-kΩ resistors are disconnected when the test conditions specify an output current of LDO1 or LDO2.
(2) With recommended usage of TPS75005, VSET does not need to be controlled on-the-fly. VSET transition time varies significantly
depending on application conditions. Stated typical value is almost the fastest transition.
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