Datasheet
SLVS167C − SEPTEMBER 1998 − REVISED − MAY 1999
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics, V
I(IN)
= 4.3 V, I
O
= 10 mA, EN = 0 V, C
O
= 4.7 µF/CSR
†
= 1 Ω, SENSE/FB
shorted to OUT (unless otherwise noted) (continued)
3.3-V regulator (TPS73HD301)
PARAMETER TEST CONDITIONS
‡
T
J
MIN TYP MAX UNIT
V
O
Output voltage
4.3 V ≤ V
I
≤ 10 V
25°C 3.3
V
V
O
Output voltage 4.3 V ≤ V
I
≤ 10 V
−40°C to 125°C 3.23 3.37
V
I
O
= 10 mA, V
I
= 3.23 V 25°C 4.5 10
Dropout voltage
I
O
= 100 mA, V
I
= 3.23 V 25°C 44 100
mV
Dropout voltage
I
O
= 750 mA, V
I
= 3.23 V
25°C 353 750
mV
I
O
= 750 mA, V
I
= 3.23 V
−40°C to 125°C 800
Pass-element series
(3.23 V − V
O
)/I
O,
V
I
= 3.23 V,
25°C 0.44 1
Ω
Pass-element series
resistance
(3.23 V − V
O
)/I
O,
V
I
= 3.23 V,
I
O
= 750 mA
−40°C to 125°C 1.07
Ω
Input regulation 50 µA ≤ I
O
≤ 750 mA, See NOTE 2 25°C 6 mV
Output regulation
I
O
= 5 mA to 750 mA, See NOTE 2 25°C 30 mV
Output regulation
I
O
= 50 µA to 750 mA, See NOTE 2
25°C 37 mV
Ripple rejection
f = 120 Hz, I
O
= 50 µA 25°C 51
dB
Ripple rejection
f = 120 Hz, I
O
= 500 mA
25°C 49
dB
Output noise-spectral density f = 120 Hz 25°C 2 mV/√Hz
10 Hz f 100 kHz,
C
L
= 4.7 µF 25°C 274
Output noise voltage
10 Hz ≤ f ≤ 100 kHz,
CSR = 1 Ω
C
L
= 10 µF 25°C 228
µV/rms
Output noise voltage
CSR = 1 Ω
C
L
= 100 µF 25°C 159
µV/rms
V
(TO)
Trip-threshold voltage
(RESET
)
V
O
decreasing −40°C to 125°C 2.868 V
V
hys
Hysteresis voltage (RESET) 25°C 18 mV
V
OL
Low-level output voltage
V
I
= 2.8 V, I
O(RESET)
= −1 mA
25°C 0.17 0.4
V
V
OL
Low-level output voltage
(RESET)
V
I
= 2.8 V, I
O(RESET)
= −1 mA
−40°C to 125°C 0.4
V
†
CSR (compensation series resistance) refers to the total series resistance, including the equivalent series resistance (ESR) of the capacitor, any
series resistance added externally, and PWB trace resistance to C
L
.
‡
Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
switching characteristics
PARAMETER TEST CONDITIONS T
J
MIN TYP MAX UNIT
Time-out delay (RESET)
See Figure 3
25°C 140 200 260
ms
Time-out delay (RESET)
See Figure 3
−40°C to 125°C 100 300
ms