Datasheet

TPS736xx
www.ti.com SBVS038T –SEPTEMBER 2003–REVISED AUGUST 2010
THERMAL INFORMATION
TPS736xx
(3)
THERMAL METRIC
(1)(2)
DRB DCQ DBV UNITS
8 PINS 6 PINS 5 PINS
q
JA
Junction-to-ambient thermal resistance
(4)
47.8 70.4 180
q
JCtop
Junction-to-case (top) thermal resistance
(5)
83 70 64
q
JB
Junction-to-board thermal resistance
(6)
N/A N/A 35
°C/W
y
JT
Junction-to-top characterization parameter
(7)
2.1 6.8 N/A
y
JB
Junction-to-board characterization parameter
(8)
17.8 30.1 N/A
q
JCbot
Junction-to-case (bottom) thermal resistance
(9)
12.1 6.3 N/A
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953A.
(2) For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.
(3) Thermal data for the DRB, DCQ, and DRV packages are derived by thermal simulations based on JEDEC-standard methodology as
specified in the JESD51 series. The following assumptions are used in the simulations:
(a) i. DRB: The exposed pad is connected to the PCB ground layer through a 2x2 thermal via array.
. ii. DCQ: The exposed pad is connected to the PCB ground layer through a 3x2 thermal via array.
. iii. DBV: There is no exposed pad with the DBV package.
(b) i. DRB: The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper
coverage.
. ii. DCQ: Each of top and bottom copper layers has a dedicated pattern for 20% copper coverage.
. iii. DBV: The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper
coverage.
(c) These data were generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3in × 3in copper area. To
understand the effects of the copper area on thermal performance, see the Power Dissipation section of this data sheet.
(4) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(5) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the top of the package. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(6) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(7) The junction-to-top characterization parameter, y
JT
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data to obtain q
JA
using a procedure described in JESD51-2a (sections 6 and 7).
(8) The junction-to-board characterization parameter, y
JB
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data to obtain q
JA
using a procedure described in JESD51-2a (sections 6 and 7).
(9) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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