Datasheet

Output Noise Dropout Voltage
Startup
V =
N
11.5
xV
OUT
mV
RMS
V
(2)
Board Layout Recommendations to Improve
Internal Current Limit
t =160 s+(540xC )
START
m
NR
nF sm
ms
nF
(3)
Shutdown
Transient Response
TPS717xx
SBVS068G FEBRUARY 2006 REVISED APRIL 2009 ..................................................................................................................................................
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In most LDOs, the bandgap is the dominant noise The TPS717xx uses a PMOS pass transistor to
source. If a noise reduction capacitor (C
NR
) is used achieve low dropout. When (V
IN
V
OUT
) is less than
with the TPS717xx, the bandgap does not contribute the dropout voltage (V
DO
), the PMOS pass device is
significantly to noise. Instead, noise is dominated by in its linear region of operation and the input-to-output
the output resistor divider and the error amplifier resistance is the R
DS(ON)
of the PMOS pass element.
input. To minimize noise in a given application, use a V
DO
will approximately scale with output current
0.01 µ F (minimum) noise reduction capacitor; for the because the PMOS device behaves like a resistor in
adjustable version, smaller value resistors in the dropout.
output resistor divider reduce noise. A parallel
As with any linear regulator, PSRR and transient
combination that gives 2.5 µ A of divider current has
response are degraded as (V
IN
V
OUT
) approaches
the same noise performance as a fixed voltage
dropout. This effect is shown in Figure 21 through
version.
Figure 23 in the Typical Characteristics section.
Equation 2 approximates the total noise referred to
the feedback point (FB pin) when C
NR
= 0.01 µ F, total
noise is approximately given by Equation 2 :
Fixed voltage versions of the TPS717xx use a
quick-start circuit to fast-charge the noise reduction
capacitor, C
NR
, if present (see Functional Block
Diagrams , Figure 1 ). This circuit allows the
combination of very low output noise and fast start-up
times. The NR pin is high impedance, so a low
PSRR and Noise Performance
leakage C
NR
capacitor must be used; most ceramic
To improve ac performance such as PSRR, output
capacitors are appropriate in this configuration.
noise, and transient response, it is recommended that
Note that for fastest startup, V
IN
should be applied
the board be designed with separate ground planes
first, then the enable pin (EN) driven high. If EN is
for V
IN
and V
OUT
, with each ground plane connected
tied to IN, startup will be somewhat slower. Refer to
only at the GND pin of the device. In addition, the
Figure 31 in the Typical Characteristics section. The
ground connection for the bypass capacitor should
quick-start switch is closed for approximately 135 µ s.
connect directly to the GND pin of the device.
To ensure that C
NR
is fully charged during the
quick-start time, a 0.01 µ F or smaller capacitor should
be used.
The TPS717xx internal current limit helps protect the
For output voltages below 1.6V, a voltage divider on
regulator during fault conditions. During current limit,
the bandgap reference voltage is employed to
the output sources a fixed amount of current that is
optimize output regulation performance for lower
largely independent of output voltage. For reliable
output voltages. This configuration results in an
operation, the device should not be operated in a
additional resistor in the quick-start path and
current limit state for extended periods of time.
combined with the noise reduction capacitor (C
NR
)
The PMOS pass element in the TPS717xx has a
results in slower start-up times for output voltages
built-in body diode that conducts current when the
below 1.6V.
voltage at OUT exceeds the voltage at IN. This
Equation 3 approximates the start-up time as a
current is not limited, so if extended reverse voltage
function of C
NR
for output voltages below 1.6V:
operation is anticipated, external limiting may be
appropriate.
The enable pin (EN) is active high and is compatible
with standard and low voltage, TTL-CMOS levels.
As with any regulator, increasing the size of the
When shutdown capability is not required, EN can be
output capacitor reduces over/undershoot magnitude
connected to IN.
but increases duration of the transient response.
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