Datasheet

Output Capacitor
C
OUT
+ 5 L
mF
mH
(7)
Layout Considerations
Thermal Information
P
D(MAX)
+
T
J(MAX)
* T
A
R
qJA
+
125°C * 85°C
48.7 °CńW
+ 820 mW
(8)
TPS63000-Q1
SLVS968 – JUNE 2009 ...................................................................................................................................................................................................... www.ti.com
For the output capacitor, it is recommended to use small ceramic capacitors placed as close as possible to the
VOUT and PGND pins of the IC. If, for any reason, the application requires the use of large capacitors which can
not be placed close to the IC, using a smaller ceramic capacitor in parallel to the large one is recommended.
This small capacitor should be placed as close as possible to the VOUT and PGND pins of the IC.
To get an estimate of the recommended minimum output capacitance, Equation 7 can be used.
A capacitor with a value in the range of the calculated minimum should be used. This is required to maintain
control loop stability. There are no additional requirements regarding minimum ESR. There is also no upper limit
for the output capacitance value. Larger capacitors will cause lower output voltage ripple as well as lower output
voltage drop during load transients.
As for all switching power supplies, the layout is an important step in the design, especially at high peak currents
and high switching frequencies. If the layout is not carefully done, the regulator could show stability problems as
well as EMI problems. Therefore, use wide and short traces for the main current path and for the power ground
tracks. The input capacitor, output capacitor, and the inductor should be placed as close as possible to the IC.
Use a common ground node for power ground and a different one for control ground to minimize the effects of
ground noise. Connect these ground nodes at any place close to one of the ground pins of the IC.
The feedback divider should be placed as close as possible to the control ground pin of the IC. To lay out the
control ground, it is recommended to use short traces as well, separated from the power ground traces. This
avoids ground shift problems, which can occur due to superimposition of power ground current and control
ground current.
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added
heat sinks and convection surfaces, and the presence of other heat-generating components affect the
power-dissipation limits of a given component.
Three basic approaches for enhancing thermal performance are listed below.
• Improving the power dissipation capability of the PCB design
• Improving the thermal coupling of the component to the PCB by soldering the Thermal Pad
• Introducing airflow in the system
The maximum recommended junction temperature (T
J
) of the TPS63000 devices is 125 ° C. The thermal
resistance of the 10-pin QFN 3 × 3 package (DRC) is R
θ JA
= 48.7 ° C/W, if the thermal pad is soldered. Specified
regulator operation is assured to a maximum ambient temperature T
A
of 85 ° C. Therefore, the maximum power
dissipation is about 820 mW, as calculated in Equation 8 . More power can be dissipated if the maximum ambient
temperature of the application is lower.
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