Datasheet

TPS62110-HT
SLVSAO9B –DECEMBER 2010–REVISED FEBRUARY 2011 www.ti.com
DETAILED DESCRIPTION (continued)
ENABLE
Logic low on EN forces the TPS62110 into shutdown. In shutdown, the power switch, drivers, voltage reference,
oscillator, and all other functions are turned off. The supply current is reduced to less than 2 μA in the shutdown
mode. When the device is in thermal shutdown, the bandgap is forced to be switched on even if the device is set
into shutdown by pulling EN to GND.
If an output voltage is present when the device is disabled, which could be due to an external voltage source or a
super capacitor, the reverse leakage current is specified under electrical characteristics. Pulling the enable pin
high starts up the TPS62110 with the soft start. If the EN pin is connected to any voltage other than V
I
or GND,
an increased leakage current of typically 10 μA and up to 20 μA can occur.
UNDERVOLTAGE LOCKOUT
The undervoltage lockout circuit prevents the device from misoperation at low-input voltages. It prevents the
converter from turning on the switch or rectifier MOSFET under undefined conditions. The minimum input voltage
to start up the TPS62110 is 3.4 V (worst case). The device shuts down at 2.8 V minimum.
SYNCHRONIZATION
If no clock signal is applied, the converter operates with a typical switching frequency of 1 MHz. It is possible to
synchronize the converter to an external clock within a frequency range from 0.8 MHz to 1.4 MHz. The device
automatically detects the rising edge of the first clock and synchronizes immediately to the external clock. If the
clock signal is stopped, the converter automatically switches back to the internal clock and continues operation.
The switch over is initiated if no rising edge on the SYNC pin is detected for a duration of four clock cycles.
Therefore, the maximum delay time can be 6.25 μs if the internal clock has its minimum frequency of 800 kHz.
If the device is synchronized to an external clock, the power save mode is disabled, and the devices stay in
forced PWM mode.
Connecting the SYNC pin to the GND pin enables the power save mode. The converter operates in the PWM
mode at moderate-to-heavy loads, and in the PFM mode during light loads, which maintains high efficiency over
a wide load current range.
POWER GOOD COMPARATOR
The power good (PG) comparator has an open-drain output capable of sinking 1 mA (typical). The PG is active
only when the device is enabled (EN=high). When the device is disabled (EN=low), the PG pin is pulled to GND.
The PG output is valid only after a 250-μs delay when the device is enabled, and the supply voltage is greater
than the undervoltage lockout V
(UVLO)
. PG is low during the first 250 μs after shutdown and in shutdown.
The PG pin becomes active high when the output voltage exceeds 98.4% (typical) of its nominal value. Leave
the PG pin unconnected when not used.
LOW-BATTERY DETECTOR
The low-battery output (LBO) is an open-drain type which goes low when the voltage at the low-battery input
(LBI) falls below the trip point of 1.256 V ±1.5%. The voltage at which the low-battery warning is issued can be
adjusted with a resistive divider as shown in Figure 11. The sum of resistors (R1 + R2) as well as the sum of (R5
+ R6) is recommended to be in the 100 kΩ to 1 MΩ range for high efficiency at low output current. An external
pullup resistor can be connected to OUT, or any other voltage rail in the voltage range of 0 V to 16 V. During
start-up, the LBO output signal is invalid for the first 500 μs. LBO is high impedance when the device is disabled.
If the low-battery comparator function is not used, connect LBI to ground. The low-battery detector is disabled
when the device is disabled.
The logic level of the LBO pin is not defined for the first 500 μs after EN is pulled high.
When the LBI is used to supervise the battery voltage and shut down the TPS62111 at low-input voltages, the
battery voltage rises when the current drops to zero. The implemented hysteresis on the LBI pin may not be
sufficient for all types of batteries. Figure 11 shows how an additional external hysteresis can be implemented.
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