Datasheet

J(MAX) S(MAX)
LIM
JC(MAX)
T T
P
R
Q
-
<
LIM
PROG
LIM
P
V
10 I
=
´
TPS2492
TPS2493
SLUSA65C –JULY 2010–REVISED JANUARY 2013 www.ti.com
VREF: Provides a 4.0-V reference voltage for use in conjunction with R4/R5 of the Typical Application Circuit to
set the voltage on the PROG pin. The reference voltage is available once the internal POR and UVLO thresholds
have been met. It is not designed as a supply voltage for other circuitry, therefore ensure that no more than 1 mA
is drawn. Bypass capacitance is not required, but if a special application requires one, less than 1000 pF can be
placed on this pin. This limit maintains VREG regulator stability.
PROG: The voltage applied to this pin (0.4 V minimum) programs the power limit used by the constant power
engine. Normally, a resistor divider R4/R5 is connected from VREF to PROG to set the power limit according to
the following equation:
(2)
where P
LIM
is the desired power limit of M1 and I
LIM
is the current limit set point (see SENSE). P
LIM
is determined
by the desired thermal stress on M1:
(3)
where T
J(MAX)
is the maximum desired transient junction temperature of M1 and T
S(MAX)
is the maximum case
temperature prior to a start or restart. V
PROG
is used in conjunction with V
DS
to compute the (scaled) current,
I
D_ALLOWED
, by the constant power engine. I
D_ALLOWED
is compared by the gate amplifier to the actual I
D
, and used
to generate a gate drive. If I
D
< I
D_ALLOWED
, the amplifier turns the gate of M1 full on because there is no overload
condition; otherwise GATE is regulated to maintain the I
D
= I
D_ALLOWED
relationship.
A capacitor may be tied from PROG to ground to alter the natural constant power inrush current shape. If
properly designed, the effect is to cause the leading step of current in Figure 13 to look like a ramp. It is not
recommended that this mechanism be used to achieve a long and low ramp inrush current because the power
limiting accuracy is lower at V
PROG
< 0.4 V. PROG is internally pulled to ground whenever UVEN, POR, or UVLO
are not satisfied or the TPS2492 is latched off. This feature serves to discharge any capacitance connected to
the pin. Do not apply voltages greater than 4 V to PROG. If the constant power limit is not used, PROG should
be tied to VREF through a 47-kΩ resistor.
TIMER: An integrating capacitor, C
T
, connected to the TIMER pin sets the fault-time for both versions and the
restart interval for the TPS2493. The timer charges at 27 µA whenever the TPS2492/3 is in power limit or current
limit and discharges at 2.7 µA otherwise. The charge-to-discharge current ratio is constant with temperature even
though there is a positive temperature coefficient to both. If V
TIMER
reaches 4 V, the TPS2492/3 pulls GATE to
ground (with the strong pull down), and discharges C
T
. The TPS2492 latches off when the fault timer expires.
The TPS2493 holds GATE at ground when the timer expires before it attempts to restart (re-enable GATE) after
a timing sequence consisting of discharging TIMER down to 1 V followed by 15 more charge and discharge
cycles. Design for the TPS2393 TIMER period must assume a 3-V rise in V
TIMER
rather than a 4-V rise to
accommodate a restart.
The TPS2492 can be reset by either cycling the UVEN pin or the UVLO (e.g. power cycling). TIMER discharges
when UVEN is low or the internal UVLO or POR are active. The TIMER pin should be tied to ground if this
feature is not used.
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