Datasheet

XCLKOUT
(/1 Mode)
XHOLD
XR/ ,
,
,
W
XZCS0AND1
XZCS2
XZCS6AND7
XD[15:0]
Valid
XHOLDA
t
d(HL-Hiz)
t
d(HH-HAH)
High-Impedance
XA[18:0]
Valid Valid
High-Impedance
t
d(HH-BV)
t
d(HL-HAL)
See Note (A) See Note (B)
TMS320F2810, TMS320F2811, TMS320F2812
TMS320C2810, TMS320C2811, TMS320C2812
www.ti.com SPRS174T –APRIL 2001–REVISED MAY 2012
6.29 XHOLD/XHOLDA Timing
Table 6-42. XHOLD/XHOLDA Timing Requirements (XCLKOUT = XTIMCLK)
(1)(2)
MIN MAX UNIT
t
d(HL-HiZ)
Delay time, XHOLD low to Hi-Z on all Address, Data, and Control 4t
c(XTIM)
ns
t
d(HL-HAL)
Delay time, XHOLD low to XHOLDA low 5t
c(XTIM)
ns
t
d(HH-HAH)
Delay time, XHOLD high to XHOLDA high 3t
c(XTIM)
ns
t
d(HH-BV)
Delay time, XHOLD high to Bus valid 4t
c(XTIM)
ns
(1) When a low signal is detected on XHOLD, all pending XINTF accesses will be completed before the bus is placed in a high-impedance
state.
(2) The state of XHOLD is latched on the rising edge of XTIMCLK.
A. All pending XINTF accesses are completed.
B. Normal XINTF operation resumes.
Figure 6-37. External Interface Hold Waveform
Copyright © 2001–2012, Texas Instruments Incorporated Electrical Specifications 141
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