Datasheet

TMS320F28030, TMS320F28031, TMS320F28032

TMS320F28033, TMS320F28034, TMS320F28035

SPRS584J –APRIL 2009–REVISED OCTOBER 2013

www.ti.com

3.2.19 32-Bit CPU-Timers (0, 1, 2)

CPU-Timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clock

prescaling. The timers have a 32-bit count-down register, which generates an interrupt when the counter

reaches zero. The counter is decremented at the CPU clock speed divided by the prescale value setting.

When the counter reaches zero, it is automatically reloaded with a 32-bit period value.

CPU-Timer 0 is for general use and is connected to the PIE block. CPU-Timer 1 is also for general use

and can be connected to INT13 of the CPU. CPU-Timer 2 is reserved for DSP/BIOS. It is connected to

INT14 of the CPU. If DSP/BIOS is not being used, CPU-Timer 2 is available for general use.

CPU-Timer 2 can be clocked by any one of the following:

• SYSCLKOUT (default)

• Internal zero-pin oscillator 1 (INTOSC1)

• Internal zero-pin oscillator 2 (INTOSC2)

• External clock source

3.2.20 Control Peripherals

The devices support the following peripherals that are used for embedded control and communication:

ePWM: The enhanced PWM peripheral supports independent/complementary PWM

generation, adjustable dead-band generation for leading/trailing edges,

latched/cycle-by-cycle trip mechanism. Some of the PWM pins support the

HRPWM high resolution duty and period features. The type 1 module found on

2803x devices also supports increased dead-band resolution, enhanced SOC and

interrupt generation, and advanced triggering including trip functions based on

comparator outputs.

eCAP: The enhanced capture peripheral uses a 32-bit time base and registers up to four

programmable events in continuous/one-shot capture modes.

This peripheral can also be configured to generate an auxiliary PWM signal.

eQEP: The enhanced QEP peripheral uses a 32-bit position counter, supports low-speed

measurement using capture unit and high-speed measurement using a 32-bit unit

timer. This peripheral has a watchdog timer to detect motor stall and input error

detection logic to identify simultaneous edge transition in QEP signals.

ADC: The ADC block is a 12-bit converter. It has up to 16 single-ended channels pinned

out, depending on the device. It contains two sample-and-hold units for

simultaneous sampling.

Comparator: Each comparator block consists of one analog comparator along with an internal

10-bit reference for supplying one input of the comparator.

HRCAP: The high-resolution capture peripheral operates in normal capture mode via a 16-

bit counter clocked off of the HCCAPCLK or in high-resolution capture mode by

utilizing built-in calibration logic in conjunction with a TI-supplied calibration library.

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Product Folder Links: TMS320F28030 TMS320F28031 TMS320F28032 TMS320F28033 TMS320F28034

TMS320F28035