Datasheet

M0 Vector RAM (Enabled if VMAP = 0)
M0 SARAM (1K x 16, 0-Wait)
0x00 0000
0x00 0040
M1 SARAM (1K x 16, 0-Wait)
0x00 0400
Data Space Prog Space
Reserved
0x00 2000
Reserved
Peripheral Frame 0
0x00 0800
Peripheral Frame 0
0x00 1580
0x00 0D00
PIE Vector - RAM
(256 x 16)
(Enabled if
VMAP = 1,
ENPIE = 1)
Peripheral Frame 0
0x00 0E00
CLA Registers
0x00 1400
CLA-to-CPU Message RAM
0x00 1480
CPU-to-CLA Message RAM
0x00 1500
0x00 8000
L0 SARAM (2K x 16)
(0-Wait, Secure Zone + ECSL, Dual-Mapped)
0x00 8800
L1 DPSARAM (1K x 16)
(0-Wait, Secure Zone + ECSL, CLA Data RAM 0)
0x00 8C00
L2 DPSARAM (1K x 16)
(0-Wait, Secure Zone + ECSL, CLA Data RAM 1)
0x00 9000
L3 DPSARAM (4K x 16)
(0-Wait, Secure Zone + ECSL, CLA Prog RAM)
0x3D 7800
User OTP (1K x 16, Secure Zone + ECSL)
0x00 A000
Reserved
0x3D 7C00
Reserved
FLASH
(32K x 16, 8 Sectors, Secure Zone + ECSL)
L0 SARAM (2K x 16)
(0-Wait, Secure Zone + ECSL, Dual-Mapped)
128-Bit Password
Boot ROM (8K x 16, 0-Wait)
Vector (32 Vectors, Enabled if VMAP = 1)
0x3D 7EB0
0x3F 0000
0x3F 7FF8
0x3F 8000
0x3F 8800
0x3F E000
0x3F FFC0
Reserved
Reserved
0x3D 7C80
Calibration Data
0x3D 7CC0
Get_mode function
0x3D 7CE0
Reserved
0x3D 7E80
PARTID
Calibration Data
Peripheral Frame 1
(1K x 16, Protected)
0x00 6000
Peripheral Frame 3
(1.5K x 16, Protected)
0x00 6400
Peripheral Frame 1
(1.5K x 16, Protected)
0x00 6A00
Peripheral Frame 2
(4K x 16, Protected)
0x00 7000
Reserved
TMS320F28030, TMS320F28031, TMS320F28032
TMS320F28033, TMS320F28034, TMS320F28035
SPRS584J –APRIL 2009–REVISED OCTOBER 2013 www.ti.com
A. CLA-specific registers and RAM apply to the 28033 device only.
B. Memory locations 0x3D7E80-0x3D7EAF are reserved in TMX silicon.
Figure 3-2. 28032/28033 Memory Map
24 Functional Overview Copyright © 2009–2013, Texas Instruments Incorporated
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Product Folder Links: TMS320F28030 TMS320F28031 TMS320F28032 TMS320F28033 TMS320F28034
TMS320F28035