! " " # $#% & Data Manual February 2004 Digital Audio Products SLES001C
Contents Section Title Page 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−1 1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−2 1.2 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−3 1.3 Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−4 1.
List of Illustrations Figure 2−1 2−2 2−3 2−4 2−5 3−1 3−2 3−3 3−4 3−5 3−6 3−7 3−8 3−9 3−10 3−11 3−12 3−13 3−14 3−15 3−16 3−17 iv Title System-Clock Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master-Mode Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Slave-Mode Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Three-Wire Control Interface Timing Requirements . . . . . . . . . . . . . . . . . .
1 Introduction The TLV320DAC23 is a high performance stereo DAC with highly integrated analog functionality. The DACs within the TLV320DAC23 are comprised of multibit sigma-delta technology with integrated over-sampling digital interpolation filters. Supported data transfer word lengths are 16, 20, 24, and 32 bits with sample rates from 8 kHz to 96 kHz. The DAC sigma-delta modulator features a second order multibit architecture with up to 100 dBA SNR at audio sample rates up to 96 kHz.
1.
1.2 Functional Block Diagram TLV320DAC23 AVDD 50 kΩ VDAC CS 1.0X Control Interface VMID 50 kΩ 1.
1.
BCLK CLKOUT BVDD DGND DVDD XTO XTI/MCLK 28 27 26 25 24 23 22 RHD PACKAGE (TOP VIEW) 4 18 CS HPVDD 5 17 LLINEIN LHPOUT 6 16 RLINEIN RHPOUT 7 15 NC AGND 14 NC NC MODE 13 19 VMID 3 12 NC 11 SDIN AVDD 20 10 2 ROUT LRCIN 9 SCLK LOUT 21 8 1 HPGND DIN NC − No internal connection 1.
1.5 Terminal Functions TERMINAL NUMBER NAME DESCRIPTION I/O GQE PW RHD AGND 5 15 12 − Analog supply return AVDD 4 14 11 − BCLK 23 3 28 I/O Analog supply input. Voltage level is 3.3 V nominal. I2S serial-bit clock. In audio master mode, the DAC23 generates this signal and sends it to the DSP. In audio slave mode, the signal is generated by the DSP. BVDD 21 1 26 − Buffer supply input. Voltage range is from 2.7 V to 3.6 V. CLKOUT 22 2 27 O Clock output.
2 Specifications 2.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range (unless otherwise noted)† Supply voltage range, AVDD to AGND, DVDD to DGND, BVDD to DGND, HPVDD to HPGND (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to + 3.63 V Analog supply return to digital supply return, AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to + 0 .
2.3 Electrical Characteristics Over Recommended Operating Conditions, AVDD, HPVDD, BVDD = 3.3 V, DVDD = 1.5 V, Master Mode, XTI = 12 MHz, (unless otherwise stated) 2.3.1 DAC 2.3.1.1 Load = 10 kΩ, 50 pF PARAMETER TEST CONDITIONS MIN TYP 90 100 0-dB full-scale output voltage Signal-to-noise ratio, A-weighted, 0-dB gain (see Notes 3, 4, and 5) Dynamic range, A-weighted (see Note 5) 1.0 AVDD = 3.3 V AVDD = 2.7 V AVDD = 3.3 V AVDD = 3.3 V Total harmonic distortion (THD) AVDD = 2.
2.3.3 Stereo Headphone Output PARAMETER TEST CONDITIONS MIN 0-dB full-scale output voltage TYP MAX 1.0 Maximum output power, PO RL = 32 Ω 30 RL = 16 Ω 40 Signal-to-noise ratio, A-weighted (see Note 4) AVDD = 3.3 V 90 Total harmonic distortion AVDD = 3.
2.4 Digital-Interface Timing PARAMETER MIN High 18 Low 18 tw(1) tw(2) System-clock pulse duration, MCLK/XTI tc(1) System-clock period, MCLK/XTI MAX Propagation delay, CLKOUT UNIT ns 54 Duty cycle, MCLK/XTI tpd(1) TYP ns 40/60% 60/40% 0 10 ns tc(1) tw(1) tw(2) MCLK/XTI tpd(1) CLKOUT CLKOUT (Div 2) Figure 2−1. System-Clock Timing Requirements 2.4.
2.4.2 Audio Interface (Slave-Mode) PARAMETER tw(3) tw(4) Pulse duration, BCLK MIN High 20 Low 20 TYP MAX UNIT ns tc(2) tsu(2) Clock period, BCLK 50 ns Setup time, DIN 10 ns th(2) tsu(3) Hold time, DIN 10 ns Setup time, LRCIN 10 ns th(3) Hold time, LRCIN 10 ns tc(2) tw(4) tw(3) BCLK LRCIN tsu(2) th(3) tsu(3) DIN th(2) Figure 2−3.
2.4.3 Three-Wire Control Interface (SDI) PARAMETER tw(5) tw(6) Clock pulse duration, SCLK MIN High 20 Low 20 TYP MAX UNIT ns tc(3) tsu(4) Clock period, SCLK 80 ns Clock rising edge to CS rising edge, SCLK 60 ns tsu(5) th(4) Setup time, SDIN to SCLK 20 ns 20 ns tw(7) tw(8) Hold time, SCLK to SDIN Pulse duration, CS High 20 Low 20 ns tw(8) CS tc(3) tw(5) tw(6) tsu(4) SCLK tsu(5) th(4) LSB DIN Figure 2−4. Three-Wire Control Interface Timing Requirements 2.4.
3 How to Use the DAC23 3.1 Control Interfaces The TLV320DAC23 has many programmable features. The control interface is used to program the registers of the device. The control interface complies with SPI (three-wire operation) and two-wire operation specifications. The state of the MODE terminal selects the control interface type. The MODE pin must be hardwired to the required level. 3.1.
The 16-bit control word is divided into two parts. The first part is the address block, the second part is the data block: B[15:9] B[8:0] Control address bits Control data bits Start Stop 1 SCLK 7 ADDR SDI 8 9 1 8 9 1 8 R/W ACK B15 − B8 ACK B7 − B0 9 ACK Figure 3−2. 2-Wire Compatible Timing 3.1.3 Register Map The TLV320DAC23 has the following set of registers, which are used to program the modes of operation.
Left Channel Headphone Volume Control (Address: 0000010) BIT D8 D7 D6 D5 D4 D3 D2 D1 D0 Function LRS LZC LHV6 LHV5 LHV4 LHV3 LHV2 LHV1 LHV0 Default 0 1 1 1 1 1 0 0 1 LRS Left/right headphone channel simultaneous volume/mute update Simultaneous update 0 = Disabled 1 = Enabled Left-channel zero-cross detect Zero-cross detect 0 = Off 1 = On Left Headphone volume control (1111001 = 0 dB default) 1111111 = +6 dB, 79 steps between +6 dB and −73 dB (mute), 0110000 = −73 dB (mute), an
Digital Audio Interface Format (Address: 0000111) BIT D8 D7 D6 D5 D4 D3 D2 D1 D0 Function X X MS LRSWAP LRP IWL1 IWL0 FOR1 FOR0 Default 0 0 0 0 0 0 0 0 1 MS LRSWAP LRP Master/slave mode DAC left/right swap DAC left/right phase IWL[1:0] FOR[1:0] Input bit length Data format X Reserved 0 = Slave 1 = Master 0 = Disabled 1 = Enabled 0 = Right channel on, LRCIN high 1 = Right channel on, LRCIN low 00 = 16 bit 01 = 20 bit 10 = 24 bit 11 = 32 bit 11 = DSP format, frame sync foll
The line inputs are biased internally to VMID. When the line inputs are muted or the device is set to standby mode, the line inputs are kept biased to VMID using special antithump circuitry. This reduces audible clicks that otherwise might be heard when reactivating the inputs. For interfacing to a CD system, the line input should be scaled to 1 VRMS to avoid clipping, using the circuit shown in Figure 3-3. Where: R1 = 5 kΩ R2 = 5 kΩ C1 = 47 pF C2 = 470 nF R1 C2 CDIN + LINEIN R 2 C1 AGND Figure 3−3.
The four modes are MSB first and operate with a variable word width between 16 to 32 bits (except right-justified mode, which does not support 32 bits). The digital audio interface consists of clock signal BCLK, data signals DIN and and the synchronization signal LRCIN. BCLK is an output in master mode and an input in slave mode. 3.3.1.1 Right-Justified Mode In right-justified mode, the LSB is available on the rising edge of BCLK, preceding a falling edge on LRCIN (see Figure 3-4).
3.3.1.4 DSP Mode The DSP mode is compatible with the McBSP ports of TI DSPs. LRCIN must be connected to the Frame Sync signal of the McBSP. A falling edge on LRCIN starts the data transfer. The left-channel data consists of the first data word, which is immediately followed by the right channel data word (see Figure 3-7). LRCIN BCLK Left Channel DIN n n−1 1 MSB Right Channel 0 n n−1 1 LSB MSB 0 LSB Figure 3−7. DSP Mode Timing 3.3.
3.3.2.1 USB-Mode Sampling Rates In the USB mode, the following DAC sampling rates are available: (MCLK = 12 MHz) SAMPLING RATE SAMPLING-RATE CONTROL SETTINGS kHz FILTER TYPE SR3 SR2 SR1 SR0 BOSR CLKIN 96 3 0 1 1 1 0 0 88.235 2 1 1 1 1 1 0 48 0 0 0 0 0 0 0 44.118 1 1 0 0 0 1 0 32 0 0 1 1 0 0 0 8.021 1 1 0 1 1 1 0 8 0 0 0 1 1 0 0 48 3 0 1 1 1 0 1 44.118 2 1 1 1 1 1 1 24 0 0 0 0 0 0 1 22.
3.3.2.2 Normal-Mode Sampling Rates In Normal mode, the following DAC sampling rates, depending on the MCLK frequency, are available: MCLK = 12.288 MHz SAMPLING RATE SAMPLING-RATE CONTROL SETTINGS kHz FILTER TYPE SR3 SR2 SR1 SR0 BOSR CLKIN 96 2 0 1 1 1 0 0 48 1 0 0 0 0 0 0 32 1 0 1 1 0 0 0 8 1 0 0 1 1 0 0 48 2 0 1 1 1 0 1 24 1 0 0 0 0 0 1 16 1 0 1 1 0 0 1 4 1 0 0 1 1 0 1 MCLK = 11.
3.3.3 Digital Filter Characteristics PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DAC Filter Characteristics (48-kHz Sampling Rate) Passband ±0.03 dB Stopband −6 dB 0.416 fs Hz 0.5 fs Hz ±0.03 Passband ripple Stopband attenuation f > 0.584 fs −50 dB dB DAC Filter Characteristics (44.1-kHz Sampling Rate) Passband ±0.03 dB Stopband −6 dB 0.4535 fs Hz 0.5 fs Stopband attenuation f > 0.5465 fs −50 0 Filter Response − dB −2 −4 −6 −8 −10 0 0.1 0.2 0.3 0.4 0.
0 Filter Response − dB −2 −4 −6 −8 −10 0 0.10 0.20 0.30 0.40 0.50 Normalized Audio Sampling Frequency − Hz Figure 3−9. Digital De-Emphasis Filter Response − 48 kHz Sampling Filter Response − dB 10 −10 −30 −50 −70 −90 0 0.5 1 1.5 2 Normalized Audio Sampling Frequency − Hz 2.5 3 Figure 3−10. DAC Digital Filter Response 0: USB Mode Filter Response − dB 0.10 0.08 0.06 0.04 0.02 0 −0.02 −0.04 −0.06 −0.08 −0.10 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.
Filter Response − dB 10 −10 −30 −50 −70 −90 0 0.5 1 1.5 2 2.5 3 Normalized Audio Sampling Frequency − Hz Figure 3−12. DAC Digital Filter Response 1: USB Mode Only Filter Response − dB 0.10 0.08 0.06 0.04 0.02 0 −0.02 −0.04 −0.06 −0.08 −0.10 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 Normalized Audio Sampling Frequency − Hz Figure 3−13. DAC Digital Filter Ripple 1: USB Mode Only Filter Response − dB 10 −10 −30 −50 −70 −90 0 0.5 1 1.5 2 2.
Filter Response − dB 0.4 0.3 0.2 0.1 0 −0.1 −0.2 −0.3 −0.4 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 Normalized Audio Sampling Frequency − Hz Figure 3−15. DAC Digital Filter Ripple 2: USB Mode and Normal Modes Filter Response − dB 10 −10 −30 −50 −70 −90 0 0.5 1 2 1.5 2.5 3 Normalized Audio Sampling Frequency − Hz Figure 3−16. DAC Digital Filter Response 3: USB Mode Only Filter Response − dB 0.4 0.3 0.2 0.1 0 −0.1 −0.2 −0.3 −0.4 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.
3−14
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE OPTION ADDENDUM www.ti.com Orderable Device TLV320DAC23RHDRG4 28-Aug-2010 Status (1) ACTIVE Package Type Package Drawing VQFN RHD Pins 28 Package Qty 3000 Eco Plan (2) Green (RoHS & no Sb/Br) Lead/ Ball Finish MSL Peak Temp (3) CU NIPDAU Level-2-260C-1 YEAR Samples (Requires Login) Request Free Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs.
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device TLV320DAC23IPWR Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 10.2 1.8 12.0 16.0 Q1 TSSOP PW 28 2000 330.0 16.4 6.9 TLV320DAC23IRHDR VQFN RHD 28 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 TLV320DAC23PWR TSSOP PW 28 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV320DAC23IPWR TSSOP PW 28 2000 367.0 367.0 38.0 TLV320DAC23IRHDR VQFN RHD 28 3000 338.1 338.1 20.6 TLV320DAC23PWR TSSOP PW 28 2000 367.0 367.0 38.0 TLV320DAC23RHDR VQFN RHD 28 3000 338.1 338.1 20.
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
