Datasheet
SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
25
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PARAMETER MEASUREMENT INFORMATION
_
+
R
null
R
L
C
L
Figure 48
APPLICATION INFORMATION
driving a capacitive load
When the amplifier is configured in this manner, capacitive loading directly on the output will decrease the
device’s phase margin leading to high frequency ringing or oscillations. Therefore, for capacitive loads of greater
than 10 pF, it is recommended that a resistor be placed in series (R
NULL
) with the output of the amplifier, as
shown in Figure 49. A minimum value of 20 Ω should work well for most applications.
C
LOAD
R
F
Input
Output
R
G
R
NULL
_
+
Figure 49. Driving a Capacitive Load
offset voltage
The output offset voltage, (V
OO
) is the sum of the input offset voltage (V
IO
) and both input bias currents (I
IB
) times
the corresponding gains. The following schematic and formula can be used to calculate the output offset
voltage:
V
OO
+ V
IO
ǒ
1 ) ǒ
R
F
R
G
Ǔ
Ǔ
" I
IB)
R
S
ǒ
1 ) ǒ
R
F
R
G
Ǔ
Ǔ
" I
IB–
R
F
+
−
V
I
+
R
G
R
S
R
F
I
IB−
V
O
I
IB+
Figure 50. Output Offset Voltage Model
Device TLV2465A is Obsolete