Datasheet

TLK3101
2.5 Gbps to 3.125 Gbps TRANSCEIVER
SCAS649B − AUGUST 2000 − REVISED JANUARY 2008
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
receive data bus (continued)
RX_CLK
RXDn, RX_DV, RX_ER
t
su
t
h
Figure 4. Receive Timing Waveform
data reception latency
The serial-to-parallel data receive latency is the time from when the first bit arrives at the receiver until it is output
in the aligned parallel word with RXD0 received as first bit. The receive latency is fixed once the link is
established. However, due to silicon process variations and implementation variables such as supply voltage
and temperature, the exact delay will vary slightly. The minimum receive latency (R
latency
) is 76 bit times; the
maximum is 107 bit times. Figure 5 illustrates the timing relationship between the serial receive pins, the
recovered word clock (RX_CLK), and the receive data bus.
16-Bit Decoded Word
20-Bit Encoded Word
DINTXP,
DINTXN
RXD(0−15)
RX_CLK
t
d(Rx latency)
Figure 5. Receiver Latency
serial to parallel
Serial data is received on the DINRXP, DINRXN pins. The interpolator and clock recovery circuit will lock to the
data stream if the clock to be recovered is within ±200 PPM of the internally generated bit rate clock. The
recovered clock is used to retime the input data stream. The serial data is then clocked into the serial-to-parallel
shift registers. The 10 bit wide parallel data is then multiplexed and fed into two separate 8-b/10-b decoders
where the data is then synchronized to the incoming data steam word boundary by detection of the K28.5
synchronization pattern.