Datasheet

TLC540I, TLC541I
8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 INPUTS
SLAS065B – OCTOBER 1983 – REVISED JUNE 2001
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
operating characteristics over recommended operating free-air temperature range,
V
CC
= V
ref+
– 4.75 V to 5.5 V, f
clock(I/O)
= 2.048 MHz for TLC540 or 1.1 MHz for TLC541,
f
clock(SYS)
= 4 MHz for TLC540 or 2.1 MHz for TLC541
PARAMETER
TEST CONDITIONS
TLC540 TLC541
UNIT
PARAMETER
TEST
CONDITIONS
MIN MAX MIN MAX
UNIT
E
L
Linearity error See Note 5 ±0.5 ±0.5 LSB
E
ZS
Zero–scale error See Notes 2 and 6 ±0.5 ±0.5 LSB
E
FS
Full-scale error See Notes 2 and 6 ±0.5 ±0.5 LSB
Total unadjusted error See Note 7 ±0.5 ±0.5 LSB
Self-test output code
Input A11 address = 1011,
(see Note 8)
01111101
(125)
10000011
(131)
01111101
(125)
10000011
(131)
t
conv
Conversion time See operating sequence 9 17 µs
Total access and conversion time See operating sequence 13.3 25 µs
t
a
Channel acquisition time (sample cycle) See operating sequence 4 4
I/O
clock
cylces
t
v
Time output data remains valid after
I/O CLOCK↓
10 10 ns
t
d
Delay time, I/O CLOCK↓ to data output
valid
300 400 ns
t
en
Output enable time
See Parameter
150 150 ns
t
dis
Output disable time
See
Parameter
Measurement Information
150 150 ns
t
r(bus)
Data bus rise time 300 300 ns
t
f(bus)
Data bus fall time 300 300 ns
NOTES: 2. Analog input voltages greater than that applied to REF+ convert to all 1s (11111111) while input voltages less than that applied to
REF– convert to all 0s (00000000). For proper operation, REF+ voltage must be at least 1 V higher than REF– voltage. Also, the
total unadjusted error may increase as this differential reference voltage falls below 4.75 V.
5. Linearity error is the maximum deviation from the best straight line through the A/D transfer characteristics.
6. Zero-scale error is the difference between 00000000 and the converted output for zero input voltage; full-scale error is the difference
between 11111111 and the converted output for full-scale input voltage.
7. Total unadjusted error is the sum of linearity, zero-scale, and full-scale errors.
8. Both the input address and the output codes are expressed in positive logic.