Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Counter Binary counter 74HC Positive slope 24 MHz SOIC 16

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  

   

SCLS039F − DECEMBER 1982 − REVISED SEPTEMBER 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D 2-V to 6-V V

Operation

D High-Current 3-State Parallel Register

Outputs Can Drive Up To 15 LSTTL Loads

D Low Power Consumption, 80-µA Max I

D Typical t

= 14 ns

D ±6-mA Output Drive at 5 V

D Low Input Current of 1 µA Max

D 8-Bit Counter With Register

D Counter Has Direct Clear

SN54HC590A ...J OR W PACKAGE

SN74HC590A . . . D, DW, OR N PACKAGE

(TOP VIEW)

SN54HC590A . . . FK PACKAGE

(TOP VIEW)

NC − No internal connection

GND

RCLK

CCKEN

CCLK

CCLR

RCO

3212019

91011 1213

RCLK

CCKEN

CCLK

RCO

CCLR

GND

description/ordering information

The ’HC590A devices contain an 8-bit binary counter that feeds an 8-bit storage register. The storage register

has parallel outputs. Separate clocks are provided for both the binary counter and storage register. The binary

counter features direct clear (CCLR

) and count-enable (CCKEN) inputs. A ripple-carry output (RCO) is provided

for cascading. Expansion is accomplished easily for two stages by connecting RCO

of the first stage to CCKEN

of the second stage. Cascading for larger count chains can be accomplished by connecting RCO of each stage

to the counter clock (CCLK) input of the following stage.

CCLK and the register clock (RCLK) inputs are positive-edge triggered. If both clocks are connected together,

the counter state always is one count ahead of the register. Internal circuitry prevents clocking from the clock

enable.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

PDIP − N Tube of 25 SN74HC590AN SN74HC590AN

Tube of 40 SN74HC590AD

−40°C to 85°C

SOIC − D

Reel of 2500 SN74HC590ADR

HC590A

−40°C to 85°C

SOIC − D

Reel of 250 SN74HC590ADT

HC590A

SOIC − DW

Tube of 40 SN74HC590ADW

HC590A

SOIC − DW

Reel of 2000 SN74HC590ADWR

HC590A

CDIP − J Tube of 25 SNJ54HC590AJ SNJ54HC590AJ

−55°C to 125°C

CFP − W Tube of 150 SNJ54HC590AW SNJ54HC590AW

−55 C to 125 C

LCCC - FK Tube of 55 SNJ54HC590AFK SNJ54HC590AFK

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design

guidelines are available at www.ti.com/sc/package.

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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Summary of content (24 pages)

PAGE 1
SCLS039F − DECEMBER 1982 − REVISED SEPTEMBER 2003 D 2-V to 6-V VCC Operation D High-Current 3-State Parallel Register Outputs Can Drive Up To 15 LSTTL Loads D Low Power Consumption, 80-µA Max ICC D Typical tpd = 14 ns 15 3 14 4 13 5 12 6 11 7 10 8 9 QD QE NC QF QG NC VCC QA QC QB VCC QA OE RCLK CCKEN CCLK CCLR RCO 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 OE RCLK NC CCKEN CCLK GND NC RCO CCLR 16
PAGE 2
SCLS039F − DECEMBER 1982 − REVISED SEPTEMBER 2003 timing diagram OE CCLR CCKEN CCLK RCLK COUNTER (internal) QA−QH ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ Don’t Care Hex 00 Don’t Care Hex 01 Hex 00 Hex 02 Hex 03 Hex 04 Hex 05 Hex FE Hex FF Hex 00 Hex01 Hi-Z Hex 01 Hex 01 RCO TIMING SEQUENCE 1. Clear Counter (asynchronous). 2. Count up: 0x01. Store 0x00 in register. 3. Inhibit counter clock (CCKEN = HIGH).
PAGE 3
SCLS039F − DECEMBER 1982 − REVISED SEPTEMBER 2003 logic diagram (positive logic) OE RCLK CCKEN CCLK CCLR 14 13 12 9 RCO 11 10 T 1R C1 1S T 1R C1 1S T 1R C1 1S T 1R C1 1S T 1R C1 1S T 1R C1 1S T 1R C1 1S T 1R C1 1S R R R R R R R R 15 1 2 3 4 5 6 7 QA QB QC QD QE QF QG QH Pin numbers shown are for the D, DW, J, N, and W packages.
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SCLS039F − DECEMBER 1982 − REVISED SEPTEMBER 2003 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 5
SCLS039F − DECEMBER 1982 − REVISED SEPTEMBER 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = −20 µA VOH VI = VIH or VIL RCO, IOH = −4 mA QA−QH, IOH = −6 mA RCO, IOH = −5.2 mA QA−QH, IOH = −7.8 mA IOL = 20 µA VOL VI = VIH or VIL RCO, IOL = 4 mA QA−QH, IOL = 6 mA RCO, IOL = 5.2 mA QA−QH, IOL = 7.
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SCLS039F − DECEMBER 1982 − REVISED SEPTEMBER 2003 timing requirements over recommended operating free-air temperature range (unless otherwise noted) VCC fclock Clock frequency CCLK or RCLK high or low tw Pulse duration CCLR low CCKEN low before CCLK↑ tsu Setup time CCLR high (inactive) before CCLK↑ CCLK↑ before RCLK↑† th Hold time CCKEN low after CCLK CCLK↑ TA = 25°C MIN MAX SN54HC590A MIN MAX SN74HC590A MIN MAX 2V 4
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SCLS039F − DECEMBER 1982 − REVISED SEPTEMBER 2003 switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) SN54HC590A PARAMETER FROM (INPUT) TO (OUTPUT) fmax tpd tPLH tpd ten tdis CCLK↑ RCO CCLR↓ RCO RCLK↑ Q OE↓ Q OE↑ Q RCO tt* Q VCC TA = 25°C MIN TYP MAX MIN 2V 4 8 2.5 4.
PAGE 8
SCLS039F − DECEMBER 1982 − REVISED SEPTEMBER 2003 switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) SN74HC590A PARAMETER FROM (INPUT) TO (OUTPUT) fmax tpd tPLH tpd ten tdis CCLK↑ CCLR↓ RCLK↑ OE↓ OE↑ RCO RCO Q Q Q RCO tt Q 8 POST OFFICE BOX 655303 VCC TA = 25°C MIN TYP MAX MIN 2V 4 8 3.2 4.
PAGE 9
SCLS039F − DECEMBER 1982 − REVISED SEPTEMBER 2003 switching characteristics over recommended operating free-air temperature range, CL = 150 pF (unless otherwise noted) (see Figure 1) SN54HC590A PARAMETER tpd ten FROM (INPUT) TO (OUTPUT) VCC TA = 25°C MIN TYP MAX 2V 100 300 447 Q 4.5 V 24 60 90 6V 20 51 77 RCLK↑ OE Q tt* Q MIN MAX 2V 90 200 300 4.5 V 23 40 60 6V 19 34 51 2V 45 210 315 4.
PAGE 10
SCLS039F − DECEMBER 1982 − REVISED SEPTEMBER 2003 PARAMETER MEASUREMENT INFORMATION VCC PARAMETER S1 Test Point From Output Under Test ten RL tPZH RL CL 50 pF or 150 pF 1 kΩ tPZL tdis S2 tPLZ 1 kΩ 50 pF −− 50 pF or 150 pF tpd or tt LOAD CIRCUIT 50% Closed Closed Open Open Closed Closed Open Open Open 50% 0V 50% tsu 0V tw Data 50% Input 10% VCC Low-Level Pulse 50% 50% 50% 0V tPLH 50% 10% tPHL 90% 9
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2013 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.
PAGE 14
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74HC590ADR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN74HC590ADWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.
PAGE 15
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74HC590ADR SN74HC590ADWR SOIC D 16 2500 333.2 345.9 28.6 SOIC DW 16 2000 367.0 367.0 38.
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