Datasheet

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APPLICATION INFORMATION
I
2
C BUS SLAVE
100 kHz
3.3 V
PCA9515A
5 V
SDA
SCL
I
2
C BUS MASTER
400 kHz
SDA1
SCL1
SDA0
SCL0
EN
SDA
SCL
BUS 0 BUS 1
9th Clock Pulse
V
OL
of PCA9515AV
OL
of Master
SCL
SDA
PCA9515A
DUAL BIDIRECTIONAL I
2
C BUS AND SMBus REPEATER
SCPS150B – DECEMBER 2005 – REVISED OCTOBER 2007
A typical application is shown in Figure 2 . In this example, the system master is running on a 3.3-V bus, while the
slave is connected to a 5-V bus. Both buses run at 100 kHz, unless the slave bus is isolated, and then the
master bus can run at 400 kHz. Master devices can be placed on either bus.
Figure 2. Typical Application
The PCA9515A is 5.5-V tolerant, so it does not require any additional circuitry to translate between the different
bus voltages.
When one side of the PCA9515A is pulled low by a device on the I
2
C bus, a CMOS hysteresis-type input detects
the falling edge and causes an internal driver on the other side to turn on, thus causing the other side also to go
low. The side driven low by the PCA9515A typically is at V
OL
= 0.5 V.
Figure 3 and Figure 4 show the waveforms that are seen in a typical application. If the bus master in Figure 2
writes to the slave through the PCA9515A, Bus 0 has the waveform shown in Figure 3 . This looks like a normal
I
2
C transmission until the falling edge of the eighth clock pulse. At that point, the master releases the data line
(SDA) while the slave pulls it low through the PCA9515A. Because the V
OL
of the PCA9515A typically is around
0.5 V, a step in the SDA is seen. After the master has transmitted the ninth clock pulse, the slave releases the
data line.
Figure 3. Bus 0 Waveforms
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