Datasheet

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I =I
Sx Lx
I
Sx
Current
Sense
I
Sx
I =10 I
Lx Sx
´
I CBusSx
2
V
CC
GND
30 W
LxBufferedBus
+
–
9 I´
Sx
Functional Description
Sx and Sy
Lx and Ly
P82B715
I
2
C BUS EXTENDER
SCPS145A – DECEMBER 2007 – REVISED FEBRUARY 2008
Figure 1. Equivalent Circuit (One-Half of P82B715)
The I
2
C pins (Sx and Sy) are designed to interface with a normal I
2
C bus. The maximum I
2
C bus supply voltage
is 12 V. The Sx and Sy pins contain identical circuitry and can be used interchangeably as SCL or SDA.
On the special low-impedance or buffered-line side, the corresponding output becomes the LDA data line or LCL
clock line. The P82B715 provides current amplification from its I
2
C bus to its low impedance or buffered bus.
Whenever current is flowing out of Sx into an I
2
C chip driving the I
2
C bus low, its amplifier sinks ten times that
current into Lx, to drive the buffered bus low (see Figure 1 ). To minimize interference and ensure stability, the
current rise and fall times of the Lx drive amplifier are internally controlled. The P82B715 does not amplify signal
currents flowing into Sx on the I
2
C bus driven by currents flowing out of Lx on the buffered side. A buffered bus
logic low signal at Lx passes via the internal 30- Ω resistor to drive the I
2
C bus low. This signal current
amplification, dependent on its direction, preserves the multimaster bidirectional open-collector/open-drain
characteristic of any connected I
2
C bus lines and the new low-impedance bus. Bus logic-signal voltage levels are
clamped at (V
CC
+ 0.7 V) but, otherwise, are independent of the supply voltage, V
CC
.
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Product Folder Link(s): P82B715