Datasheet
OPA549
SBOS093E
9
www.ti.com
FIGURE 2. Adjustable Current Limit.
ENABLE/STATUS (E/S) PIN
The Enable/Status Pin provides two unique functions:
1) output disable by forcing the pin low, and 2) thermal
shutdown indication by monitoring the voltage level at the
pin. Either or both of these functions can be utilized in an
application. For normal operation (output enabled), the E/S
pin can be left open or driven high (at least 2.4V above Ref).
A small value capacitor connected between the E/S pin and
C
REF
may be required for noisy applications.
Output Disable
To disable the output, the E/S pin is pulled to a logic low (no
greater than 0.8V above Ref). Typically the output is shut down
in 1µs. To return the output to an enabled state, the E/S pin
should be disconnected (open) or pulled to at least 2.4V above
Ref. It should be noted that driving the E/S pin high (output
enabled)
does not defeat internal thermal shutdown
; however,
it does prevent the user from monitoring the thermal shutdown
status. Figure 3 shows an example implementing this function.
This function not only conserves power during idle periods
(quiescent current drops to approximately 6mA) but also allows
multiplexing in multi-channel applications. See Figure 12 for two
OPA549s in a switched amplifier configuration. The on/off state
of the two amplifiers is controlled by the voltage on the E/S pin.
Under these conditions, the disabled device will behave like a
750pF load. Slewing faster than 3V/µs will cause leakage
current to rapidly increase in devices that are disabled, and will
contribute additional load. At high temperature (125°C), the
slewing threshold drops to approximately 2V/µs. Input signals
must be limited to avoid excessive slewing in multiplexed
applications.
FIGURE 3. Output Disable.
OPA549
E/S
CMOS or TTL
Ref
Logic
Ground
7500Ω
R
CL
0.01µF
(optional, for noisy
environments)
8
6
8
6
4.75V
R
CL
=
– 7500Ω
OPA549 CURRENT LIMIT: 0A to 10A
NOTES: (1) Resistors are nearest standard 1% values. (2) Offset in the current limit circuitry
may introduce approximately ±0.25A variation at low current limit values.
DESIRED
CURRENT LIMIT
0A
(2)
2.5A
3A
4A
5A
6A
7A
8A
9A
10A
RESISTOR
(1)
(R
CL
)
I
LIM
Open
22.6kΩ
17.4kΩ
11.3kΩ
7.5kΩ
4.99kΩ
3.24kΩ
1.87kΩ
845Ω
I
LIM
Connected to Ref
CURRENT
(I
SET
)
0µA
158µA
190µA
253µA
316µA
380µA
443µA
506µA
570µA
633µA
VOLTAGE
(V
SET
)
(Ref) + 4.75V
(Ref) + 3.56V
(Ref) + 3.33V
(Ref) + 2.85V
(Ref) + 2.38V
(Ref) + 1.90V
(Ref) + 1.43V
(Ref) + 0.95V
(Ref) + 0.48V
(Ref)
(a) RESISTOR METHOD
15800 (4.75V)
I
LIM
=
– 7.5kΩ
75kΩ
I
LIM
7500Ω
I
SET
= I
LIM
/15800
V
SET
= (Ref) + 4.75V – (7500Ω) (I
LIM
)/15800
(b) DAC METHOD (Current or Voltage)
D/A
I
SET
4.75V
Ref
Ref
±I
LIM
=
Max I
O
= I
LIM
(4.75) (15800)
7500Ω + R
CL
Max I
O
= I
LIM
±I
LIM
=15800 I
SET