Datasheet

www.ti.com SD24_A Operation
27.2.12.3 SD24_A Interrupt Handling Software Example
The following software example shows the recommended use of SD24IV and the handling overhead. The
SD24IV value is added to the PC to automatically jump to the appropriate routine.
The numbers at the right margin show the necessary CPU cycles for each instruction. The software
overhead for different interrupt sources includes interrupt latency and return-from-interrupt cycles, but not
the task handling itself. The latencies are:
• SD24OVIFG, CH0 SD24IFG, CH1 SD24IFG: 16 cycles
• CH2 SD24IFG: 14 cycles
The interrupt handler for channel 2 SD24IFG shows a way to check immediately if a higher prioritized
interrupt occurred during the processing of the ISR. This saves nine cycles if another SD24_A interrupt is
pending.
; Interrupt handler for SD24_A.
INT_SD24 ; Enter Interrupt Service Routine 6
ADD &SD24IV,PC ; Add offset to PC 3
RETI ; Vector 0: No interrupt 5
JMP ADOV ; Vector 2: ADC overflow 2
JMP ADM0 ; Vector 4: CH_0 SD24IFG 2
JMP ADM1 ; Vector 6: CH_1 SD24IFG 2
;
; Handler for CH_2 SD24IFG starts here. No JMP required.
;
ADM2 MOV &SD24MEM2,xxx ; Move result, flag is reset
... ; Other instruction needed?
JMP INT_SD24 ; Check other int pending 2
;
; Remaining Handlers
;
ADM1 MOV &SD24MEM1,xxx ; Move result, flag is reset
... ; Other instruction needed?
RETI ; Return 5
;
ADM0 MOV &SD24MEM0,xxx ; Move result, flag is reset
RETI ; Return 5
;
ADOV ... ; Handle SD24MEMx overflow
RETI ; Return 5
631
SLAU144J–December 2004–Revised July 2013 SD24_A
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