Datasheet

DV
CC
DV
SS
AV
CC
AV
SS
Ve
REF+
Digital
Power Supply
Decoupling
10 uF 100 nF
+
Using an External
Positive
Reference
V
REF+
V
REF−
/ Ve
REF−
Using the Internal
Reference
Generator
10 uF 100 nF
100 nF
+
+
10 uF 100 nF
+
Using an External
Negative
Reference
10 uF
+
Analog
Power Supply
Decoupling
10 uF 100 nF
ADC12 Operation www.ti.com
Figure 23-11. ADC12 Grounding and Noise Considerations
23.2.9 ADC12 Interrupts
The ADC12 has 18 interrupt sources:
• ADC12IFG0 to ADC12IFG15
• ADC12OV, ADC12MEMx overflow
• ADC12TOV, ADC12 conversion time overflow
The ADC12IFGx bits are set when their corresponding ADC12MEMx memory register is loaded with a
conversion result. An interrupt request is generated if the corresponding ADC12IEx bit and the GIE bit are
set. The ADC12OV condition occurs when a conversion result is written to any ADC12MEMx before its
previous conversion result was read. The ADC12TOV condition is generated when another sample-and-
conversion is requested before the current conversion is completed. The DMA is triggered after the
conversion in single channel modes or after the completion of a sequence-of-channel modes.
23.2.9.1 ADC12IV, Interrupt Vector Generator
All ADC12 interrupt sources are prioritized and combined to source a single interrupt vector. The interrupt
vector register ADC12IV is used to determine which enabled ADC12 interrupt source requested an
interrupt.
The highest priority enabled ADC12 interrupt generates a number in the ADC12IV register (see
Section 23.3.7). This number can be evaluated or added to the program counter to automatically enter the
appropriate software routine. Disabled ADC12 interrupts do not affect the ADC12IV value.
Any access (read or write) of the ADC12IV register automatically resets the ADC12OV condition or the
ADC12TOV condition if either was the highest pending interrupt. Neither interrupt condition has an
accessible interrupt flag. The ADC12IFGx flags are not reset by an ADC12IV access. ADC12IFGx bits are
reset automatically by accessing their associated ADC12MEMx register or may be reset with software.
If another interrupt is pending after servicing of an interrupt, another interrupt is generated. For example, if
the ADC12OV and ADC12IFG3 interrupts are pending when the interrupt service routine accesses the
ADC12IV register, the ADC12OV interrupt condition is reset automatically. After the RETI instruction of the
interrupt service routine is executed, the ADC12IFG3 generates another interrupt.
572
ADC12 SLAU144J–December 2004–Revised July 2013
Submit Documentation Feedback
Copyright © 2004–2013, Texas Instruments Incorporated