Datasheet

www.ti.com USCI Registers: I
2
C Mode
17.4.2 UCBxCTL1, USCI_Bx Control Register 1
7 6 5 4 3 2 1 0
UCSSELx Unused UCTR UCTXNACK UCTXSTP UCTXSTT UCSWRST
rw-0 rw-0 r0 rw-0 rw-0 rw-0 rw-0 rw-1
UCSSELx Bits 7-6 USCI clock source select. These bits select the BRCLK source clock.
00 UCLKI
01 ACLK
10 SMCLK
11 SMCLK
Unused Bit 5 Unused
UCTR Bit 4 Transmitter/receiver
0 Receiver
1 Transmitter
UCTXNACK Bit 3 Transmit a NACK. UCTXNACK is automatically cleared after a NACK is transmitted.
0 Acknowledge normally
1 Generate NACK
UCTXSTP Bit 2 Transmit STOP condition in master mode. Ignored in slave mode. In master receiver mode the STOP
condition is preceded by a NACK. UCTXSTP is automatically cleared after STOP is generated.
0 No STOP generated
1 Generate STOP
UCTXSTT Bit 1 Transmit START condition in master mode. Ignored in slave mode. In master receiver mode a repeated
START condition is preceded by a NACK. UCTXSTT is automatically cleared after START condition and
address information is transmitted. Ignored in slave mode.
0 Do not generate START condition
1 Generate START condition
UCSWRST Bit 0 Software reset enable
0 Disabled. USCI reset released for operation.
1 Enabled. USCI logic held in reset state.
17.4.3 UCBxBR0, USCI_Bx Baud Rate Control Register 0
7 6 5 4 3 2 1 0
UCBRx - low byte
rw rw rw rw rw rw rw rw
17.4.4 UCBxBR1, USCI_Bx Baud Rate Control Register 1
7 6 5 4 3 2 1 0
UCBRx - high byte
rw rw rw rw rw rw rw rw
UCBRx Bit clock prescaler setting. The 16-bit value of (UCBxBR0 + UCBxBR1 × 256) forms the prescaler value.
469
SLAU144J–December 2004–Revised July 2013
Universal Serial Communication Interface, I
2
C Mode
Submit Documentation Feedback
Copyright © 2004–2013, Texas Instruments Incorporated