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USCI Registers: UART Mode

15.4.1 UCAxCTL0, USCI_Ax Control Register 0

7 6 5 4 3 2 1 0

UCPEN UCPAR UCMSB UC7BIT UCSPB UCMODEx UCSYNC

rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0

UCPEN Bit 7 Parity enable

0 Parity disabled.

1 Parity enabled. Parity bit is generated (UCAxTXD) and expected (UCAxRXD). In address-bit

multiprocessor mode, the address bit is included in the parity calculation.

UCPAR Bit 6 Parity select. UCPAR is not used when parity is disabled.

0 Odd parity

1 Even parity

UCMSB Bit 5 MSB first select. Controls the direction of the receive and transmit shift register.

0 LSB first

1 MSB first

UC7BIT Bit 4 Character length. Selects 7-bit or 8-bit character length.

0 8-bit data

1 7-bit data

UCSPB Bit 3 Stop bit select. Number of stop bits.

0 One stop bit

1 Two stop bits

UCMODEx Bits 2-1 USCI mode. The UCMODEx bits select the asynchronous mode when UCSYNC = 0.

00 UART mode

01 Idle-line multiprocessor mode

10 Address-bit multiprocessor mode

11 UART mode with automatic baud rate detection

UCSYNC Bit 0 Synchronous mode enable

0 Asynchronous mode

1 Synchronous mode

429

SLAU144J–December 2004–Revised July 2013 Universal Serial Communication Interface, UART Mode

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