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Before

Interrupt

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Interrupt

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Interrupts

2.2.3 Interrupt Processing

When an interrupt is requested from a peripheral and the peripheral interrupt enable bit and GIE bit are

set, the interrupt service routine is requested. Only the individual enable bit must be set for (non)-

maskable interrupts to be requested.

2.2.3.1 Interrupt Acceptance

The interrupt latency is 5 cycles (CPUx) or 6 cycles (CPU), starting with the acceptance of an interrupt

request and lasting until the start of execution of the first instruction of the interrupt-service routine, as

shown in Figure 2-6. The interrupt logic executes the following:

1. Any currently executing instruction is completed.

2. The PC, which points to the next instruction, is pushed onto the stack.

3. The SR is pushed onto the stack.

4. The interrupt with the highest priority is selected if multiple interrupts occurred during the last

instruction and are pending for service.

5. The interrupt request flag resets automatically on single-source flags. Multiple source flags remain set

for servicing by software.

6. The SR is cleared. This terminates any low-power mode. Because the GIE bit is cleared, further

interrupts are disabled.

7. The content of the interrupt vector is loaded into the PC: the program continues with the interrupt

service routine at that address.

Figure 2-6. Interrupt Processing

SLAU144J–December 2004–Revised July 2013 System Resets, Interrupts, and Operating Modes

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