Datasheet

DMA Registers www.ti.com
6.3.5 DMAxDA, DMA Destination Address Register
15 14 13 12 11 10 9 8
Reserved
r0 r0 r0 r0 r0 r0 r0 r0
7 6 5 4 3 2 1 0
Reserved DMAxDAx
r0 r0 r0 r0 rw rw rw rw
15 14 13 12 11 10 9 8
DMAxDAx
rw rw rw rw rw rw rw rw
7 6 5 4 3 2 1 0
DMAxDAx
rw rw rw rw rw rw rw rw
DMAxDA Bits 15-0
DMA destination address
The destination address register points to the DMA destination address for single transfers or the first
destination address for block transfers. The destination address register remains unchanged during block
and burst-block transfers.
Devices that have addressable memory range 64 KB or below contain a single word for the DMAxDA.
Devices that have addressable memory range beyond 64 KB contain an additional word for the destination
address. Bits 15-4 of this additional word are reserved and always read as zero. When writing to DMAxDA
with word formats, this additional word is automatically cleared. Reads of this additional word using word
formats, are always read as zero.
6.3.6 DMAxSZ, DMA Size Address Register
15 14 13 12 11 10 9 8
DMAxSZx
rw rw rw rw rw rw rw rw
7 6 5 4 3 2 1 0
DMAxSZx
rw rw rw rw rw rw rw rw
DMAxSZx Bits 15-0 DMA size. The DMA size register defines the number of byte/word data per block transfer. DMAxSZ register
decrements with each word or byte transfer. When DMAxSZ decrements to 0, it is immediately and
automatically reloaded with its previously initialized value.
00000h Transfer is disabled
00001h One byte or word to be transferred
00002h Two bytes or words have to be transferred
⋮
0FFFFh 65535 bytes or words have to be transferred
306
DMA Controller SLAU144J–December 2004–Revised July 2013
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