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Table 6-2. DMA Trigger Operation (continued)
DMAxTSELx Operation
0101 A transfer is triggered when the DAC12_0CTL DAC12IFG flag is set. The DAC12_0CTL DAC12IFG flag is
automatically cleared when the transfer starts. If the DAC12_0CTL DAC12IE bit is set, the DAC12_0CTL
DAC12IFG flag will not trigger a transfer.
0110 A transfer is triggered by an ADC12IFGx flag. When single-channel conversions are performed, the
corresponding ADC12IFGx is the trigger. When sequences are used, the ADC12IFGx for the last conversion
in the sequence is the trigger. A transfer is triggered when the conversion is completed and the ADC12IFGx is
set. Setting the ADC12IFGx with software will not trigger a transfer. All ADC12IFGx flags are automatically
reset when the associated ADC12MEMx register is accessed by the DMA controller.
0111 A transfer is triggered when the TACCR0 CCIFG flag is set. The TACCR0 CCIFG flag is automatically reset
when the transfer starts. If the TACCR0 CCIE bit is set, the TACCR0 CCIFG flag will not trigger a transfer.
1000 A transfer is triggered when the TBCCR0 CCIFG flag is set. The TBCCR0 CCIFG flag is automatically reset
when the transfer starts. If the TBCCR0 CCIE bit is set, the TBCCR0 CCIFG flag will not trigger a transfer.
1001 A transfer is triggered when the UCA1RXIFG flag is set. UCA1RXIFG is automatically reset when the transfer
starts. If URXIE1 is set, the UCA1RXIFG flag will not trigger a transfer.
1010 A transfer is triggered when the UCA1TXIFG flag is set. UCA1TXIFG is automatically reset when the transfer
starts. If UTXIE1 is set, the UCA1TXIFG flag will not trigger a transfer.
1011 A transfer is triggered when the hardware multiplier is ready for a new operand.
1100
No transfer is triggered.
Devices with USCI_B0 module: A transfer is triggered when USCI_B0 receives new data. UCB0RXIFG is
automatically reset when the transfer starts. If UCB0RXIE is set, the UCB0RXIFG flag will not trigger a
transfer.
1101
No transfer is triggered.
Devices with USCI_B0 module: A transfer is triggered when USCI_B0 is ready to transmit new data.
UCB0TXIFG is automatically reset when the transfer starts. If UCB0TXIE is set, the UCB0TXIFG flag will not
trigger a transfer.
1110 A transfer is triggered when the DMAxIFG flag is set. DMA0IFG triggers channel 1, DMA1IFG triggers
channel 2, and DMA2IFG triggers channel 0. None of the DMAxIFG flags are automatically reset when the
transfer starts.
1111 A transfer is triggered by the external trigger DMAE0.
6.2.4 Stopping DMA Transfers
There are two ways to stop DMA transfers in progress:
• A single, block, or burst-block transfer may be stopped with an NMI interrupt, if the ENNMI bit is set in
register DMACTL1.
• A burst-block transfer may be stopped by clearing the DMAEN bit.
298
DMA Controller SLAU144J–December 2004–Revised July 2013
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