Datasheet

C
19 0
MSB0 - - - - - - - - - - - - - - - - - - - - 0
7
LSB
C
19 0
MSB LSB
8
C
15 0
MSB LSB
19 16
0 0 0 0
0
0
0
Instruction Set Description www.ti.com
4.6.3.30 RRUX
RRUX.A Shift right unsigned the 20-bit CPU register content
RRUX.[W] Shift right unsigned the 16-bit CPU register content
RRUX.B Shift right unsigned the 8-bit CPU register content
RRUX.A Rdst
Syntax
RRUX.W Rdst
RRUX Rdst
RRUX.B Rdst
Operation C=0 → MSB → MSB–1 ... LSB+1 → LSB → C
Description RRUX is valid for register mode only: the destination operand is shifted right by one bit
position as shown in Figure 4-53. The word instruction RRUX.W clears the bits
Rdst.19:16. The byte instruction RRUX.B clears the bits Rdst.19:8. Zero is shifted into
the MSB, the LSB is shifted into the carry bit.
Status Bits N: Set if result is negative
.A: dst.19 = 1, reset if dst.19 = 0
.W: dst.15 = 1, reset if dst.15 = 0
.B: dst.7 = 1, reset if dst.7 = 0
Z: Set if result is zero, reset otherwise
C: Loaded from the LSB
V: Reset
Mode Bits OSCOFF, CPUOFF, and GIE are not affected.
Example The word in R6 is shifted right by 12 positions.
RPT #12
RRUX.W R6 ; R6 = R6 » 12. R6.19:16 = 0
Figure 4-53. Rotate Right Unsigned RRUX(.B,.A) – Register Mode
248
CPUX SLAU144J–December 2004–Revised July 2013
Submit Documentation Feedback
Copyright © 2004–2013, Texas Instruments Incorporated