Datasheet

MF10-N
SNOS547C –JUNE 1999–REVISED APRIL 2013 www.ti.com
Resistive Divider with Operational Amplifier
Decoupling Capacitor Voltage Regulator with Divider
Figure 34. Three Ways of Generating V
+
/2 for Single-Supply Operation
SINGLE SUPPLY OPERATION
The MF10-N can also operate with a single-ended power supply. Figure 33 shows the example filter with a
single-ended power supply. V
A
+
and V
D
+
are again connected to the positive power supply (8V to 14V), and V
A
−
and V
D
−
are connected to ground. The A
GND
pin must be tied to V
+
/2 for single supply operation. This half-supply
point should be very “clean”, as any noise appearing on it will be treated as an input to the filter. It can be derived
from the supply voltage with a pair of resistors and a bypass capacitor (See Figure 34), or a low-impedance half-
supply voltage can be made using a three-terminal voltage regulator or an operational amplifier (See Figure 34
and Figure 34). The passive resistor divider with a bypass capacitor is sufficient for many applications, provided
that the time constant is long enough to reject any power supply noise. It is also important that the half-supply
reference present a low impedance to the clock frequency, so at very low clock frequencies the regulator or op-
amp approaches may be preferable because they will require smaller capacitors to filter the clock frequency. The
main power supply voltage should be clean (preferably regulated) and bypassed with 0.1 μF.
DYNAMIC CONSIDERATIONS
The maximum signal handling capability of the MF10-N, like that of any active filter, is limited by the power
supply voltages used. The amplifiers in the MF10-N are able to swing to within about 1V of the supplies, so the
input signals must be kept small enough that none of the outputs will exceed these limits. If the MF10-N is
operating on ±5V, for example, the outputs will clip at about 8 V
p–p
. The maximum input voltage multiplied by the
filter gain should therefore be less than 8 V
p–p
.
Note that if the filter Q is high, the gain at the lowpass or highpass outputs will be much greater than the nominal
filter gain (Figure 22). As an example, a lowpass filter with a Q of 10 will have a 20 dB peak in its amplitude
response at f
O
. If the nominal gain of the filter H
OLP
is equal to 1, the gain at f
O
will be 10. The maximum input
signal at f
O
must therefore be less than 800 mV
p–p
when the circuit is operated on ±5V supplies.
Also note that one output can have a reasonable small voltage on it while another is saturated. This is most likely
for a circuit such as the notch in Mode 1 (Figure 23). The notch output will be very small at f
O
, so it might appear
safe to apply a large signal to the input. However, the bandpass will have its maximum gain at f
O
and can clip if
overdriven. If one output clips, the performance at the other outputs will be degraded, so avoid overdriving any
filter section, even ones whose outputs are not being directly used. Accompanying Figure 23 through Figure 31
are equations labeled “circuit dynamics”, which relate the Q and the gains at the various outputs. These should
be consulted to determine peak circuit gains and maximum allowable signals for a given application.
OFFSET VOLTAGE
The MF10-N's switched capacitor integrators have a higher equivalent input offset voltage than would be found in
a typical continuous-time active filter integrator. Figure 35 shows an equivalent circuit of the MF10-N from which
the output DC offsets can be calculated. Typical values for these offsets with S
A/B
tied to V
+
are:
V
os1
= opamp offset = ±5 mV
V
os2
= −150 mV @ 50:1 −300 mV @ 100:1
V
os3
= −70 mV @ 50:1 −140 mV @ 100:1
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