Datasheet

LP38501-ADJ, LP38503-ADJ

SNVS522H –AUGUST 2007–REVISED APRIL 2013

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SETTING THE OUTPUT VOLTAGE

The output voltage of the LP38501/3-ADJ can be set to any value between 0.6V and 5V using two external

resistors shown as R1 and R2 in Figure 15.

Figure 15.

The value of R2 should always be less than or equal to 10 kΩ for good loop compensation. R1 can be selected

for a given V

OUT

using the following formula:

OUT

= V

ADJ

(1 + R1/R2) + I

ADJ

(R1)

where

• V

ADJ

is the adjust pin voltage

• I

ADJ

is the bias current flowing into the adjust pin (1)

STABILITY AND PHASE MARGIN

Any regulator which operates using a feedback loop must be compensated in such a way as to ensure adequate

phase margin, which is defined as the difference between the phase shift and -180 degrees at the frequency

where the loop gain crosses unity (0 dB). For most LDO regulators, the ESR of the output capacitor is required to

create a zero to add enough phase lead to ensure stable operation. The LP38501 has a unique internal

compensation circuit which maintains phase margin regardless of the ESR of the output capacitor, so any type of

capacitor may be used.

Figure 16 shows the gain/phase plot of the LP38501-ADJ with an output of 1.2V, 10 µF ceramic output capacitor,

delivering 2A of load current. It can be seen that the unity-gain crossover occurs at 300 kHz, and the phase

margin is about 40° (which is very stable).

Figure 16. Gain-Bandwidth Plot for 2A Load

Figure 17 shows the gain and phase with no external load. In this case, the only load is provided by the gain

setting resistors (about 12 kΩ total in this test). It is immediately obvious that the unity-gain frequency is

significantly lower (dropping to about 500 Hz), at which point the phase margin is 125°.

Product Folder Links: LP38501-ADJ LP38503-ADJ