Datasheet

LM5642, LM5642X

SNVS219K –JUNE 2003–REVISED APRIL 2013

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Output Capacitor Selection

In applications that exhibit large, fast load current swings, the slew rate of such a load current transient will likely

be beyond the response speed of the regulator. Therefore, to meet voltage transient requirements during worst-

case load transients, special consideration should be given to output capacitor selection. The total combined

ESR of the output capacitors must be lower than a certain value, while the total capacitance must be greater

than a certain value. Also, in applications where the specification of output voltage regulation is tight and ripple

voltage must be low, starting from the required output voltage ripple will often result in fewer design iterations.

ALLOWED TRANSIENT VOLTAGE EXCURSION

The allowed output voltage excursion during a load transient (ΔVc_s) is:

where

• ±δ% is the output voltage regulation window

• ±ε% is the output voltage initial accuracy (10)

Example: Vnom = 5V, δ% = 7%, ε% = 3.4%, Vrip = 40mV peak to peak.

(11)

MAXIMUM ESR CALCULATION

Unless the rise and fall times of a load transient are slower than the response speed of the control loop, if the

total combined ESR (Re) is too high, the load transient requirement will not be met, no matter how large the

capacitance.

The maximum allowed total combined ESR is:

(12)

Since the ripple voltage is included in the calculation of ΔVc_s, the inductor ripple current should not be included

in the worst-case load current excursion. Simply use the worst-case load current excursion for ΔIc_s.

Example: ΔVc_s = 160 mV, ΔIc_s = 3A. Then Re_max = 53.3 mΩ.

Maximum ESR criterion can be used when the associated capacitance is high enough, otherwise more

capacitors than the number determined by this criterion should be used in parallel.

MINIMUM CAPACITANCE CALCULATION

In a switch mode power supply, the minimum output capacitance is typically dictated by the load transient

requirement. If there is not enough capacitance, the output voltage excursion will exceed the maximum allowed

value even if the maximum ESR requirement is met. The worst-case load transient is an unloading transient that

happens when the input voltage is the highest and when the current switching cycle has just finished. The

corresponding minimum capacitance is calculated as follows:

(13)

Notice it is already assumed the total ESR, Re, is no greater than Re_max, otherwise the term under the square

root will be a negative value. Also, it is assumed that L has already been selected, therefore the minimum L

value should be calculated before C

min

and after Re (see Inductor Selection below). Example: Re = 20 mΩ,

Vnom = 5V, ΔVc_s = 160 mV, ΔIc_s = 3A, L = 8 µH

(14)

Generally speaking, C

min

decreases with decreasing Re, ΔIc_s, and L, but with increasing Vnom and ΔVc_s.

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