Datasheet

LM3150
SNVS561D –SEPTEMBER 2008–REVISED MARCH 2011 www.ti.com
10. C
VCC
, C
EN
, and C
BST
C
VCC
= 4.7 µF ceramic with a voltage rating greater than 10V
C
EN
= 1000 pF ceramic with a voltage rating greater than 10V
C
BST
= 0.47 µF ceramic with a voltage rating greater than 10V
Bill of Materials
Designator Value Parameters Manufacturer Part Number
C
BST
0.47 µF Ceramic, X7R, 16V, 10% TDK C2012X7R1C474K
C
BYP
0.1 µF Ceramic, X7R, 50V, 10% TDK C2012X7R1H104K
C
EN
1000 pF Ceramic, X7R, 50V, 10% TDK C1608X7R1H102K
C
FF
270 pF Ceramic, C0G, 50V, 5% Vishay-Bccomponents VJ0805A271JXACW1BC
C
IN1
, C
IN2
10 µF Ceramic, X5R, 35V, 20% Taiyo Yuden GMK325BJ106KN-T
C
OUT1
, C
OUT2
150 µF Polymer Aluminum, , 6.3V, 20% Panasonic EEF-UE0J151R
C
SS
0.068 µF Ceramic, 0805, 25V, 10% Vishay VJ0805Y683KXXA
C
VCC
4.7 µF Ceramic, X7R, 16V, 10% Murata GRM21BR71C475KA73L
L1 1.65 µH Shielded Drum Core, 2.53 mΩ Coilcraft HA3778–AL
M1, M2 30V 8 nC, R
DS(ON)
@4.5V=10 mΩ Renesas RJK0305DPB
R
FB1
4.99 kΩ 1%, 0.125W Vishay-Dale CRCW08054k99FKEA
R
FB2
22.6 kΩ 1%, 0.125W Vishay-Dale CRCW080522k6FKEA
R
LIM
1.91 kΩ 1%, 0.125W Vishay-Dale CRCW08051K91FKEA
R
ON
56.2 kΩ 1%, 0.125W Vishay-Dale CRCW080556K2FKEA
U1 LM3150 Texas Instruments LM3150MH
PCB Layout Considerations
It is good practice to layout the power components first, such as the input and output capacitors, FETs, and
inductor. The first priority is to make the loop between the input capacitors and the source of the low-side FET to
be very small and tie the grounds of the low-side FET and input capacitor directly to each other and then to the
ground plane through vias. As shown in Figure 17 when the input capacitor ground is tied directly to the source
of the low-side FET, parasitic inductance in the power path, along with noise coupled into the ground plane, are
reduced.
The switch node is the next item of importance. The switch node should be made only as large as required to
handle the load current. There are fast voltage transitions occurring in the switch node at a high frequency, and if
the switch node is made too large it may act as an antennae and couple switching noise into other parts of the
circuit. For high power designs, it is recommended to use a multi-layer board. The FETs are going to be the
largest heat generating devices in the design, and as such, care should be taken to remove the heat. On multi-
layer boards using exposed-pad packages for the FETs such as the power-pak SO-8, vias should be used under
the FETs to the same plane on the interior layers to help dissipate the heat and cool the FETs. For the typical
single FET Power-Pak type FETs, the high-side FET DAP is V
IN
. The V
IN
plane should be copied to the other
interior layers to the bottom layer for maximum heat dissipation. Likewise, the DAP of the low-side FET is
connected to the SW node and the SW node shape should be duplicated to the other PCB layers for maximum
heat dissipation.
See the Evaluation Board application note AN-1900 (SNVA371) for an example of a typical multi-layer board
layout, and the Demonstration Board Reference Design Application Note for a typical 2 layer board layout. Each
design allows for single sided component mounting.
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