Datasheet

REF LEVEL
0.000 dB
0.0 deg
100 1k
START 100.000 Hz
10k
STOP 100 000.000 Hz
/DIV
10.000 dB
45.000 deg
100k
GAIN
PHASE
0
LM25574, LM25574-Q1
SNVS483G –JANUARY 2007–REVISED APRIL 2013 www.ti.com
Capacitor C2 provides filtering for the divider. The voltage at the SD pin should never exceed 8V, when using an
external set-point divider it may be necessary to clamp the SD pin at high input voltage conditions. The reference
design utilizes the full range of the LM25574 (6V to 42V); therefore these components can be omitted. With the
SD pin open circuit the LM25574 responds once the Vcc UVLO threshold is satisfied.
R4, C5, C6
These components configure the error amplifier gain characteristics to accomplish a stable overall loop gain. One
advantage of current mode control is the ability to close the loop with only two feedback components, R4 and C5.
The overall loop gain is the product of the modulator gain and the error amplifier gain. The DC modulator gain of
the LM25574 is as follows:
DC Gain
(MOD)
= G
m(MOD)
x R
LOAD
= 0.5 x R
LOAD
(13)
The dominant low frequency pole of the modulator is determined by the load resistance (R
LOAD
,) and output
capacitance (C
OUT
). The corner frequency of this pole is:
f
p(MOD)
= 1 / (2π R
LOAD
C
OUT
) (14)
For R
LOAD
= 20Ω and C
OUT
= 22µF then f
p(MOD)
= 362Hz
DC Gain
(MOD)
= 0.5 x 20 = 20dB
For the design example of Typical Application Circuit and Block Diagram the following modulator gain vs.
frequency characteristic was measured as shown in Figure 16.
Figure 16. Gain and Phase of Modulator R
LOAD
= 20 Ohms and C
OUT
= 22µF
Components R4 and C5 configure the error amplifier as a type II configuration which has a pole at DC and a
zero at f
Z
= 1 / (2πR4C5). The error amplifier zero cancels the modulator pole leaving a single pole response at
the crossover frequency of the loop gain. A single pole response at the crossover frequency yields a very stable
loop with 90 degrees of phase margin.
For the design example, a target loop bandwidth (crossover frequency) of 25kHz was selected. The
compensation network zero (f
Z
) should be selected at least an order of magnitude less than the target crossover
frequency. This constrains the product of R4 and C5 for a desired compensation network zero 1 / (2π R4 C5) to
be less than 2kHz. Increasing R4, while proportionally decreasing C5, increases the error amp gain. Conversely,
decreasing R4 while proportionally increasing C5, decreases the error amp gain. For the design example C5 was
selected for 0.022µF and R4 was selected for 24.9kΩ. These values configure the compensation network zero at
290Hz. The error amp gain at frequencies greater than f
Z
is: R4 / R5, which is approximately 5 (14dB).
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