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COMPARATOR DELAY (14-Pin Version Only)
C
DELAY
(in mF) +
t
D
5
(4)
REFERENCE
COMPARATOR
U2
U1
0.6V
1.2V
I2
120nA
I1
120nA
C
DELAY
0V
0.6V
V
IN
CMP Out
RESET
INA206
INA207
INA208
SBOS360E – JUNE 2006 – REVISED OCTOBER 2007
Note that the specified accuracy of the INA206,
INA207, and INA208 must then be combined in
The Comparator 2 programmable delay is controlled
addition to these tolerances. While this discussion
by a capacitor connected to the CMP2 Delay Pin; see
treated accuracy worst-case conditions by combining
Figure 30 . The capacitor value (in μ F) is selected by
the extremes of the resistor values, it is appropriate to
using Equation 4 :
use geometric mean or root sum square calculations
to total the effects of accuracy variations.
A simplified version of the delay circuit for
Comparator 2 is shown in Figure 34 . The delay
The INA206, INA207, and INA208 include an internal
comparator consists of two comparator stages with
voltage reference that has a load regulation of
the delay between them. Note that I1 and I2 cannot
0.4mV/mA (typical), and not more than 100ppm/ ° C of
be turned on simultaneously; I1 corresponds to a U1
drift. Only the 14-pin package allows external access
low output and I2 corresponds to a U1 high output.
to reference voltages, where voltages of 1.2V and
Using an initial assumption that the U1 output is low,
0.6V are both available. Output current versus output
I1 is on, then U2 +IN is zero. If U1 goes high, I2
voltage is illustrated in the Typical Characteristics
supplies 120nA to C
DELAY
. The voltage at U2 +IN
section.
begins to ramp toward a 0.6V threshold. When the
voltage crosses this threshold, the U2 output goes
high while the voltage at U2 +IN continues to ramp up
The INA206, INA207, and INA208 devices
to a maximum of 1.2V when given sufficient time
incorporate two open-drain comparators. These
(twice the value of the delay specified for C
DELAY
).
comparators typically have 2mV of offset and a 1.3 μ s
This entire sequence is reversed when the
(typical) response time. The output of Comparator 1
comparator outputs go low, so that returning to low
latches and is reset through the CMP1 RESET pin,
exhibits the same delay.
as shown in Figure 35 . This configuration applies to
both the 10- and 14-pin versions. Figure 34 illustrates
the comparator delay.
The 14-pin versions of the INA206, INA207, and
INA208 include additional features for comparator
functions. The comparator reference voltage of both
Comparator 1 and Comparator 2 can be overridden
by external inputs for increased design flexibility.
Comparator 2 has a programmable delay.
Figure 34. Simplified Model of the Comparator 2
Delay Circuit
Figure 35. Comparator 1 Latching Capability
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