Datasheet
DS92LV090A
SNLS025D –APRIL 2000–REVISED APRIL 2013
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APPLICATIONS INFORMATION
General application guidelines and hints may be found in the following application notes: AN-808 (SNLA028),
AN-903 (SNLA034), AN-971 (SNLA165), AN-977 (SNLA166), and AN-1108 (SNLA008).
There are a few common practices which should be implied when designing PCB for Bus LVDS signaling.
Recommended practices are:
• Use at least 4 PCB board layer (Bus LVDS signals, ground, power and TTL signals).
• Keep drivers and receivers as close to the (Bus LVDS port side) connector as possible.
• Bypass each Bus LVDS device and also use distributed bulk capacitance between power planes. Surface
mount capacitors placed close to power and ground pins work best. Two or three high frequency, multi-layer
ceramic (MLC) surface mount (0.1 µF, 0.01 µF, 0.001 µF) in parallel should be used between each V
CC
and
ground. The capacitors should be as close as possible to the V
CC
pin.
– Multiple vias should be used to connect V
CC
and Ground planes to the pads of the by-pass capacitors.
– In addition, randomly distributed by-pass capacitors should be used.
• Use the termination resistor which best matches the differential impedance of your transmission line.
• Leave unused Bus LVDS receiver inputs open (floating). Limit traces on unused inputs to <0.5 inches.
• Isolate TTL signals from Bus LVDS signals
MEDIA (CONNECTOR or BACKPLANE) SELECTION:
• Use controlled impedance media. The backplane and connectors should have a matched differential
impedance.
Table 1. Functional Table
MODE SELECTED DE RE
DRIVER MODE H H
RECEIVER MODE L L
TRI-STATE MODE L H
LOOP BACK MODE H L
Table 2. Transmitter Mode
INPUTS OUTPUTS
DE D
IN
DO+ DO−
H L L H
H H H L
H 0.8V< D
IN
<2.0V X X
L X Z Z
Table 3. Receiver Mode
(1)
INPUTS OUTPUT
RE (RI+) – (RI−)
L L (< −100 mV) L
L H (> +100 mV) H
L −100 mV < V
ID
< +100 mV X
H X Z
(1) X = High or Low logic state
L = Low state
Z = High impedance state
H = High state
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