Datasheet

MSB
X X PD1 PD0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DATA BITS
0 0 Normal Operation.
0 1 2.5kÖ to GND.
1 0 100kÖ to GND.
1 1 High Impedance.
LSB
Power-Down Modes
D7 D6 D5 D4 D3 D2 D1 D0
1 9 1 9
ACK
by
DAC121C081
Start by
Master
NACK
by
Master
SCL
SDA
Stop by
Master
1 9
0 0 PD1 PD0 D11 D10 D9 D8
ACK
by
Master
Frame 1
Address Byte
from Master
Frame 2
Data Byte from
DAC121C081
Frame 3
Data Byte from
DAC121C081
R/W
A2 A0A1A3A4A5A6
DAC121C081, DAC121C085
www.ti.com SNAS395D –DECEMBER 2007–REVISED MARCH 2013
Figure 24. Typical Read from the DAC Register
DAC REGISTER
The DAC register, Figure 25, has sixteen bits. The first two bits are always zero. The next two bits determine the
mode of operation (normal mode or one of three power-down modes). The final twelve bits of the shift register
are the data bits. The data format is straight binary (MSB first, LSB last), with twelve 0's corresponding to an
output of 0V and twelve 1's corresponding to a full-scale output of V
A
- 1 LSB. When writing to the DAC Register,
V
OUT
will update on the rising edge of the ACK following the lower data byte.
Figure 25. DAC Register Contents
POWER-ON RESET
The power-on reset circuit controls the output voltage of the DAC during power-up. Upon application of power,
the DAC register is filled with zeros and the output voltage is 0 Volts. The output remains at 0V until a valid write
sequence is made to the DAC.
When resetting the device, it is crutial that the V
A
supply be lowered to a maximum of 200mV before the supply
is raised again to power-up the device. Dropping the supply to within 200mV of GND during a reset will ensure
the ADC performs as specified.
SIMULTANEOUS RESET
The broadcast address allows the I
2
C master to write a single word to multiple DACs simultaneously. Provided
that all of the DACs exist on a single I
2
C bus, every DAC will update when the broadcast address is used to
address the bus. This feature allows the master to reset all of the DACs on a shared I
2
C bus to a specific digital
code. For instance, if the master writes a power-down code to the bus with the broadcast address, all of the
DACs will power-down simultaneously.
POWER-DOWN MODES
The DAC121C081 has three power-down modes. In power-down mode, the supply current drops to 0.13µA at 3V
and 0.15µA at 5V (typ). The DAC121C081 is put into power-down mode by writing a one to PD1 and/or PD0.
The outputs can be set to high impedance, terminated by 2.5 kΩ to GND, or terminated by 100 kΩ to GND (see
Figure 25).
The bias generator, output amplifier, resistor string, and other linear circuitry are all shut down in any of the
power-down modes. When the DAC121C081 is powered down, the value written to the DAC register, including
the power-down bits, is saved. While the DAC is in power-down, the saved DAC register contents can be read
back. When the DAC is brought out of power-down mode, the DAC register contents will be overwritten and V
OUT
will be updated with the new 12-bit data value.
The time to exit power-down (Wake-Up Time) is typically 0.8µsec at 3V and 0.5µsec at 5V.
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