Datasheet

-6 -4 -2 0 2 4 6
V , INPUT SIGNAL VOLTAGE (V)
IS
V
OS
, OUTPUT SIGNAL VOLTAGE (V)
-6
-4
-2
0
2
4
6
V = 5V
DD
V = 0V
SS
V = -5V
EE
T = 25 C
A
o
R = 100k , R = 10k
L L
Ω Ω
100Ω
500Ω
1kΩ
19
CD4051B , CD4052B , CD4053B
www.ti.com SCHS047I –AUGUST 1998–REVISED SEPTEMBER 2017
Product Folder Links: CD4051B CD4052B CD4053B
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Typical Application (continued)
9.2.2 Detailed Design Procedure
1. Recommended Input Conditions
– For switch time specifications, see propagation delay times in Electrical Characteristics.
– Inputs should not be pushed more than 0.5 V above V
DD
or below V
EE
.
– For input voltage level specifications for control inputs, see V
IH
and V
IL
in Electrical Characteristics.
2. Recommended Output Conditions
– Outputs should not be pulled above V
DD
or below V
EE
.
3. Input/output current consideration: The CD405xB series of parts do not have internal current drive circuitry
and thus cannot sink or source current. Any current will be passed through the device.
9.2.3 Application Curve
Figure 30. ON Characteristics for 1 of 8 Channels
(CD4051B)
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Electrical Characteristics.
Each V
CC
terminal should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, a 0.1-μF bypass capacitor is recommended. If there are multiple pins labeled V
CC
, then a 0.01-μF or
0.022-μF capacitor is recommended for each V
CC
because the V
CC
pins will be tied together internally. For
devices with dual supply pins operating at different voltages, for example V
CC
and V
DD
, a 0.1-µF bypass
capacitor is recommended for each supply pin. It is acceptable to parallel multiple bypass capacitors to reject
different frequencies of noise. 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor
should be installed as close to the power terminal as possible for best results.